1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#ifndef __ARCH_ARM_ISA_HH__
44#define __ARCH_MRM_ISA_HH__
45
46#include "arch/arm/registers.hh"
47#include "arch/arm/types.hh"
48
49class ThreadContext;
50class Checkpoint;
51class EventManager;
52
53namespace ArmISA
54{
55 class ISA
56 {
57 protected:
58 MiscReg miscRegs[NumMiscRegs];
59 const IntRegIndex *intRegMap;
60
61 void
62 updateRegMap(CPSR cpsr)
63 {
64 switch (cpsr.mode) {
65 case MODE_USER:
66 case MODE_SYSTEM:
67 intRegMap = IntRegUsrMap;
68 break;
69 case MODE_FIQ:
70 intRegMap = IntRegFiqMap;
71 break;
72 case MODE_IRQ:
73 intRegMap = IntRegIrqMap;
74 break;
75 case MODE_SVC:
76 intRegMap = IntRegSvcMap;
77 break;
78 case MODE_MON:
79 intRegMap = IntRegMonMap;
80 break;
81 case MODE_ABORT:
82 intRegMap = IntRegAbtMap;
83 break;
84 case MODE_UNDEFINED:
85 intRegMap = IntRegUndMap;
86 break;
87 default:
88 panic("Unrecognized mode setting in CPSR.\n");
89 }
90 }
91
92 public:
93 void clear()
94 {
95 memset(miscRegs, 0, sizeof(miscRegs));
96 CPSR cpsr = 0;
97 cpsr.mode = MODE_USER;
98 miscRegs[MISCREG_CPSR] = cpsr;
99 updateRegMap(cpsr);
100
101 SCTLR sctlr = 0;
102 sctlr.nmfi = 1;
103 sctlr.rao1 = 1;
104 sctlr.rao2 = 1;
105 sctlr.rao3 = 1;
106 sctlr.rao4 = 1;
107 miscRegs[MISCREG_SCTLR] = sctlr;
108
109 /*
110 * Technically this should be 0, but we don't support those
111 * settings.
112 */
113 miscRegs[MISCREG_CPACR] = 0x0fffffff;
114
115 //XXX We need to initialize the rest of the state.
116 }
117
118 MiscReg
119 readMiscRegNoEffect(int misc_reg)
120 {
121 assert(misc_reg < NumMiscRegs);
122 if (misc_reg == MISCREG_SPSR) {
123 CPSR cpsr = miscRegs[MISCREG_CPSR];
124 switch (cpsr.mode) {
125 case MODE_USER:
126 return miscRegs[MISCREG_SPSR];
127 case MODE_FIQ:
128 return miscRegs[MISCREG_SPSR_FIQ];
129 case MODE_IRQ:
130 return miscRegs[MISCREG_SPSR_IRQ];
131 case MODE_SVC:
132 return miscRegs[MISCREG_SPSR_SVC];
133 case MODE_MON:
134 return miscRegs[MISCREG_SPSR_MON];
135 case MODE_ABORT:
136 return miscRegs[MISCREG_SPSR_ABT];
137 case MODE_UNDEFINED:
138 return miscRegs[MISCREG_SPSR_UND];
139 default:
140 return miscRegs[MISCREG_SPSR];
141 }
142 }
143 return miscRegs[misc_reg];
144 }
145
146 MiscReg
147 readMiscReg(int misc_reg, ThreadContext *tc)
148 {
149 if (misc_reg == MISCREG_CPSR) {
150 CPSR cpsr = miscRegs[misc_reg];
151 Addr pc = tc->readPC();
152 if (pc & (ULL(1) << PcJBitShift))
153 cpsr.j = 1;
154 else
155 cpsr.j = 0;
156 if (pc & (ULL(1) << PcTBitShift))
157 cpsr.t = 1;
158 else
159 cpsr.t = 0;
160 return cpsr;
161 }
162 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
163 misc_reg < MISCREG_CP15_END) {
164 panic("Unimplemented CP15 register %s read.\n",
165 miscRegName[misc_reg]);
166 }
167 return readMiscRegNoEffect(misc_reg);
168 }
169
170 void
171 setMiscRegNoEffect(int misc_reg, const MiscReg &val)
172 {
173 assert(misc_reg < NumMiscRegs);
174 if (misc_reg == MISCREG_SPSR) {
175 CPSR cpsr = miscRegs[MISCREG_CPSR];
176 switch (cpsr.mode) {
177 case MODE_USER:
178 miscRegs[MISCREG_SPSR] = val;
179 return;
180 case MODE_FIQ:
181 miscRegs[MISCREG_SPSR_FIQ] = val;
182 return;
183 case MODE_IRQ:
184 miscRegs[MISCREG_SPSR_IRQ] = val;
185 return;
186 case MODE_SVC:
187 miscRegs[MISCREG_SPSR_SVC] = val;
188 return;
189 case MODE_MON:
190 miscRegs[MISCREG_SPSR_MON] = val;
191 return;
192 case MODE_ABORT:
193 miscRegs[MISCREG_SPSR_ABT] = val;
194 return;
195 case MODE_UNDEFINED:
196 miscRegs[MISCREG_SPSR_UND] = val;
197 return;
198 default:
199 miscRegs[MISCREG_SPSR] = val;
200 return;
201 }
202 }
203 miscRegs[misc_reg] = val;
204 }
205
206 void
207 setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
208 {
209 MiscReg newVal = val;
210 if (misc_reg == MISCREG_CPSR) {
211 updateRegMap(val);
212 CPSR cpsr = val;
213 Addr npc = tc->readNextPC() & ~PcModeMask;
214 if (cpsr.j)
215 npc = npc | (ULL(1) << PcJBitShift);
216 if (cpsr.t)
217 npc = npc | (ULL(1) << PcTBitShift);
218
219 tc->setNextPC(npc);
220 }
221 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
222 misc_reg < MISCREG_CP15_END) {
223 panic("Unimplemented CP15 register %s wrote with %#x.\n",
224 miscRegName[misc_reg], val);
225 }
226 switch (misc_reg) {
227 case MISCREG_CPACR:
228 newVal = bits(val, 27, 0);
229 if (newVal != 0x0fffffff) {
230 panic("Disabling coprocessors isn't implemented.\n");
231 }
232 break;
233 }
234 return setMiscRegNoEffect(misc_reg, newVal);
235 }
236
237 int
238 flattenIntIndex(int reg)
239 {
240 assert(reg >= 0);
241 if (reg < NUM_ARCH_INTREGS) {
242 return intRegMap[reg];
243 } else if (reg < NUM_INTREGS) {
244 return reg;
245 } else {
246 reg -= NUM_INTREGS;
247 assert(reg < NUM_ARCH_INTREGS);
248 return reg;
249 }
250 }
251
252 int
253 flattenFloatIndex(int reg)
254 {
255 return reg;
256 }
257
258 void serialize(EventManager *em, std::ostream &os)
259 {}
260 void unserialize(EventManager *em, Checkpoint *cp,
261 const std::string &section)
262 {}
263
264 ISA()
265 {
266 clear();
267 }
268 };
269}
270
271#endif