1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#ifndef __ARCH_ARM_ISA_HH__
44#define __ARCH_MRM_ISA_HH__
45
46#include "arch/arm/registers.hh"
47#include "arch/arm/types.hh"
48
49class ThreadContext;
50class Checkpoint;
51class EventManager;
52
53namespace ArmISA
54{

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218 switch (misc_reg) {
219 case MISCREG_CLIDR:
220 warn("The clidr register always reports 0 caches.\n");
221 break;
222 case MISCREG_CCSIDR:
223 warn("The ccsidr register isn't implemented and "
224 "always reads as 0.\n");
225 break;
226 }
227 return readMiscRegNoEffect(misc_reg);
228 }
229
230 void
231 setMiscRegNoEffect(int misc_reg, const MiscReg &val)
232 {
233 assert(misc_reg < NumMiscRegs);

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342 return;
343 }
344 case MISCREG_TLBTR:
345 case MISCREG_MVFR0:
346 case MISCREG_MVFR1:
347 case MISCREG_MPIDR:
348 case MISCREG_FPSID:
349 return;
350 }
351 setMiscRegNoEffect(misc_reg, newVal);
352 }
353
354 int
355 flattenIntIndex(int reg)
356 {
357 assert(reg >= 0);

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