1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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129 (0xf << 16) | //Architecture from CPUID scheme
130 (0 << 4) | //Primary part number
131 (0 << 0) | //Revision
132 0;
133
134 // Separate Instruction and Data TLBs.
135 miscRegs[MISCREG_TLBTR] = 1;
136
137 //XXX We need to initialize the rest of the state.
138 }
139
140 MiscReg
141 readMiscRegNoEffect(int misc_reg)
142 {
143 assert(misc_reg < NumMiscRegs);
144 if (misc_reg == MISCREG_SPSR) {

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268 }
269 newVal = newCpacr;
270 }
271 break;
272 case MISCREG_CSSELR:
273 warn("The csselr register isn't implemented.\n");
274 break;
275 case MISCREG_TLBTR:
276 return;
277 }
278 return setMiscRegNoEffect(misc_reg, newVal);
279 }
280
281 int
282 flattenIntIndex(int reg)
283 {

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