1/*
2 * Copyright (c) 2010, 2012-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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43#ifndef __ARCH_ARM_ISA_HH__
44#define __ARCH_ARM_ISA_HH__
45
46#include "arch/arm/isa_device.hh"
47#include "arch/arm/registers.hh"
48#include "arch/arm/system.hh"
49#include "arch/arm/tlb.hh"
50#include "arch/arm/types.hh"
51#include "debug/Checkpoint.hh"
52#include "sim/sim_object.hh"
53#include "enums/DecoderFlavour.hh"
54
55struct ArmISAParams;
56struct DummyArmISADeviceParams;
57class ThreadContext;
58class Checkpoint;
59class EventManager;
60
61namespace ArmISA
62{
63 class ISA : public SimObject
64 {
65 protected:
66 // Parent system
67 ArmSystem *system;
68
69 // Micro Architecture
70 const Enums::DecoderFlavour _decoderFlavour;
71
72 /** Dummy device for to handle non-existing ISA devices */
73 DummyISADevice dummyDevice;
74
75 // PMU belonging to this ISA
76 BaseISADevice *pmu;
77
78 // Generic timer interface belonging to this ISA

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180 RegId
181 flattenRegId(const RegId& regId) const
182 {
183 switch (regId.classValue()) {
184 case IntRegClass:
185 return RegId(IntRegClass, flattenIntIndex(regId.index()));
186 case FloatRegClass:
187 return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
188 case CCRegClass:
189 return RegId(CCRegClass, flattenCCIndex(regId.index()));
190 case MiscRegClass:
191 return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
192 }
193 return RegId();
194 }
195

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228 int
229 flattenFloatIndex(int reg) const
230 {
231 assert(reg >= 0);
232 return reg;
233 }
234
235 int
236 flattenCCIndex(int reg) const
237 {
238 assert(reg >= 0);
239 return reg;
240 }
241
242 int
243 flattenMiscIndex(int reg) const

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401 UNSERIALIZE_SCALAR(haveLargeAsid64);
402 UNSERIALIZE_SCALAR(physAddrRange64);
403 }
404
405 void startup(ThreadContext *tc) {}
406
407 Enums::DecoderFlavour decoderFlavour() const { return _decoderFlavour; }
408
409 /// Explicitly import the otherwise hidden startup
410 using SimObject::startup;
411
412 typedef ArmISAParams Params;
413
414 const Params *params() const;
415
416 ISA(Params *p);
417 };
418}
419
420#endif