1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#ifndef __ARCH_ARM_ISA_HH__
44#define __ARCH_MRM_ISA_HH__
45
46#include "arch/arm/registers.hh"
47#include "arch/arm/types.hh"
48
49class ThreadContext;
50class Checkpoint;
51class EventManager;
52
53namespace ArmISA
54{
55 class ISA
56 {
57 protected:
58 MiscReg miscRegs[NumMiscRegs];
59 const IntRegIndex *intRegMap;
60
61 void
62 updateRegMap(CPSR cpsr)
63 {
64 switch (cpsr.mode) {
65 case MODE_USER:
66 case MODE_SYSTEM:
67 intRegMap = IntRegUsrMap;
68 break;
69 case MODE_FIQ:
70 intRegMap = IntRegFiqMap;
71 break;
72 case MODE_IRQ:
73 intRegMap = IntRegIrqMap;
74 break;
75 case MODE_SVC:
76 intRegMap = IntRegSvcMap;
77 break;
78 case MODE_MON:
79 intRegMap = IntRegMonMap;
80 break;
81 case MODE_ABORT:
82 intRegMap = IntRegAbtMap;
83 break;
84 case MODE_UNDEFINED:
85 intRegMap = IntRegUndMap;
86 break;
87 default:
88 panic("Unrecognized mode setting in CPSR.\n");
89 }
90 }
91
92 public:
93 void clear()
94 {
95 memset(miscRegs, 0, sizeof(miscRegs));
96 CPSR cpsr = 0;
97 cpsr.mode = MODE_USER;
98 miscRegs[MISCREG_CPSR] = cpsr;
99 updateRegMap(cpsr);
100
101 SCTLR sctlr = 0;
102 sctlr.nmfi = 1;
103 sctlr.rao1 = 1;
104 sctlr.rao2 = 1;
105 sctlr.rao3 = 1;
106 sctlr.rao4 = 1;
107
108 //XXX We need to initialize the rest of the state.
109 }
110
111 MiscReg
112 readMiscRegNoEffect(int misc_reg)
113 {
114 assert(misc_reg < NumMiscRegs);
115 if (misc_reg == MISCREG_SPSR) {
116 CPSR cpsr = miscRegs[MISCREG_CPSR];
117 switch (cpsr.mode) {
118 case MODE_USER:
119 return miscRegs[MISCREG_SPSR];
120 case MODE_FIQ:
121 return miscRegs[MISCREG_SPSR_FIQ];
122 case MODE_IRQ:
123 return miscRegs[MISCREG_SPSR_IRQ];
124 case MODE_SVC:
125 return miscRegs[MISCREG_SPSR_SVC];
126 case MODE_MON:
127 return miscRegs[MISCREG_SPSR_MON];
128 case MODE_ABORT:
129 return miscRegs[MISCREG_SPSR_ABT];
130 case MODE_UNDEFINED:
131 return miscRegs[MISCREG_SPSR_UND];
132 default:
133 return miscRegs[MISCREG_SPSR];
134 }
135 }
136 return miscRegs[misc_reg];
137 }
138
139 MiscReg
140 readMiscReg(int misc_reg, ThreadContext *tc)
141 {
142 if (misc_reg == MISCREG_CPSR) {
143 CPSR cpsr = miscRegs[misc_reg];
144 Addr pc = tc->readPC();
145 if (pc & (ULL(1) << PcJBitShift))
146 cpsr.j = 1;
147 else
148 cpsr.j = 0;
149 if (pc & (ULL(1) << PcTBitShift))
150 cpsr.t = 1;
151 else
152 cpsr.t = 0;
153 return cpsr;
154 }
155 return readMiscRegNoEffect(misc_reg);
156 }
157
158 void
159 setMiscRegNoEffect(int misc_reg, const MiscReg &val)
160 {
161 assert(misc_reg < NumMiscRegs);
162 if (misc_reg == MISCREG_SPSR) {
163 CPSR cpsr = miscRegs[MISCREG_CPSR];
164 switch (cpsr.mode) {
165 case MODE_USER:
166 miscRegs[MISCREG_SPSR] = val;
167 return;
168 case MODE_FIQ:
169 miscRegs[MISCREG_SPSR_FIQ] = val;
170 return;
171 case MODE_IRQ:
172 miscRegs[MISCREG_SPSR_IRQ] = val;
173 return;
174 case MODE_SVC:
175 miscRegs[MISCREG_SPSR_SVC] = val;
176 return;
177 case MODE_MON:
178 miscRegs[MISCREG_SPSR_MON] = val;
179 return;
180 case MODE_ABORT:
181 miscRegs[MISCREG_SPSR_ABT] = val;
182 return;
183 case MODE_UNDEFINED:
184 miscRegs[MISCREG_SPSR_UND] = val;
185 return;
186 default:
187 miscRegs[MISCREG_SPSR] = val;
188 return;
189 }
190 }
191 miscRegs[misc_reg] = val;
192 }
193
194 void
195 setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
196 {
197 if (misc_reg == MISCREG_CPSR) {
198 updateRegMap(val);
199 CPSR cpsr = val;
200 Addr npc = tc->readNextPC() & ~PcModeMask;
201 if (cpsr.j)
202 npc = npc | (ULL(1) << PcJBitShift);
203 if (cpsr.t)
204 npc = npc | (ULL(1) << PcTBitShift);
205
206 tc->setNextPC(npc);
207 }
208 return setMiscRegNoEffect(misc_reg, val);
209 }
210
211 int
212 flattenIntIndex(int reg)
213 {
214 assert(reg >= 0);
215 if (reg < NUM_ARCH_INTREGS) {
216 return intRegMap[reg];
217 } else if (reg < NUM_INTREGS) {
218 return reg;
219 } else {
220 reg -= NUM_INTREGS;
221 assert(reg < NUM_ARCH_INTREGS);
222 return reg;
223 }
224 }
225
226 int
227 flattenFloatIndex(int reg)
228 {
229 return reg;
230 }
231
232 void serialize(EventManager *em, std::ostream &os)
233 {}
234 void unserialize(EventManager *em, Checkpoint *cp,
235 const std::string &section)
236 {}
237
238 ISA()
239 {
240 clear();
241 }
242 };
243}
244
245#endif