isa.cc (9377:6f294e7a93d1) | isa.cc (9384:877293183bdf) |
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1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 29 unchanged lines hidden (view full) --- 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "arch/arm/system.hh" 43#include "cpu/checker/cpu.hh" 44#include "debug/Arm.hh" 45#include "debug/MiscRegs.hh" | 1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 29 unchanged lines hidden (view full) --- 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "arch/arm/system.hh" 43#include "cpu/checker/cpu.hh" 44#include "debug/Arm.hh" 45#include "debug/MiscRegs.hh" |
46#include "params/ArmISA.hh" |
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46#include "sim/faults.hh" 47#include "sim/stat_control.hh" 48#include "sim/system.hh" 49 50namespace ArmISA 51{ 52 | 47#include "sim/faults.hh" 48#include "sim/stat_control.hh" 49#include "sim/system.hh" 50 51namespace ArmISA 52{ 53 |
54ISA::ISA(Params *p) 55 : SimObject(p) 56{ 57 SCTLR sctlr; 58 sctlr = 0; 59 miscRegs[MISCREG_SCTLR_RST] = sctlr; 60 clear(); 61} 62 63const ArmISAParams * 64ISA::params() const 65{ 66 return dynamic_cast<const Params *>(_params); 67} 68 |
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53void 54ISA::clear() 55{ 56 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 57 uint32_t midr = miscRegs[MISCREG_MIDR]; 58 memset(miscRegs, 0, sizeof(miscRegs)); 59 CPSR cpsr = 0; 60 cpsr.mode = MODE_USER; --- 575 unchanged lines hidden (view full) --- 636 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 637 miscRegName[misc_reg], uint32_t(val)); 638 } 639 } 640 setMiscRegNoEffect(misc_reg, newVal); 641} 642 643} | 69void 70ISA::clear() 71{ 72 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 73 uint32_t midr = miscRegs[MISCREG_MIDR]; 74 memset(miscRegs, 0, sizeof(miscRegs)); 75 CPSR cpsr = 0; 76 cpsr.mode = MODE_USER; --- 575 unchanged lines hidden (view full) --- 652 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 653 miscRegName[misc_reg], uint32_t(val)); 654 } 655 } 656 setMiscRegNoEffect(misc_reg, newVal); 657} 658 659} |
660 661ArmISA::ISA * 662ArmISAParams::create() 663{ 664 return new ArmISA::ISA(this); 665} |
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