isa.cc (8887:20ea02da9c53) isa.cc (9050:ed4378739b6e)
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "arch/arm/system.hh"
42#include "cpu/checker/cpu.hh"
43#include "debug/Arm.hh"
44#include "debug/MiscRegs.hh"
45#include "sim/faults.hh"
46#include "sim/stat_control.hh"
47#include "sim/system.hh"
48
49namespace ArmISA

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67 sctlr.u = 1;
68 sctlr.xp = 1;
69 sctlr.rao2 = 1;
70 sctlr.rao3 = 1;
71 sctlr.rao4 = 1;
72 miscRegs[MISCREG_SCTLR] = sctlr;
73 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
74
43#include "cpu/checker/cpu.hh"
44#include "debug/Arm.hh"
45#include "debug/MiscRegs.hh"
46#include "sim/faults.hh"
47#include "sim/stat_control.hh"
48#include "sim/system.hh"
49
50namespace ArmISA

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68 sctlr.u = 1;
69 sctlr.xp = 1;
70 sctlr.rao2 = 1;
71 sctlr.rao3 = 1;
72 sctlr.rao4 = 1;
73 miscRegs[MISCREG_SCTLR] = sctlr;
74 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
75
75 // Preserve MIDR accross reset
76 // Preserve MIDR across reset
76 miscRegs[MISCREG_MIDR] = midr;
77
78 /* Start with an event in the mailbox */
79 miscRegs[MISCREG_SEV_MAILBOX] = 1;
80
81 // Separate Instruction and Data TLBs.
82 miscRegs[MISCREG_TLBTR] = 1;
83

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97 mvfr1.defaultNaN = 1;
98 mvfr1.advSimdLoadStore = 1;
99 mvfr1.advSimdInteger = 1;
100 mvfr1.advSimdSinglePrecision = 1;
101 mvfr1.advSimdHalfPrecision = 1;
102 mvfr1.vfpHalfPrecision = 1;
103 miscRegs[MISCREG_MVFR1] = mvfr1;
104
77 miscRegs[MISCREG_MIDR] = midr;
78
79 /* Start with an event in the mailbox */
80 miscRegs[MISCREG_SEV_MAILBOX] = 1;
81
82 // Separate Instruction and Data TLBs.
83 miscRegs[MISCREG_TLBTR] = 1;
84

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98 mvfr1.defaultNaN = 1;
99 mvfr1.advSimdLoadStore = 1;
100 mvfr1.advSimdInteger = 1;
101 mvfr1.advSimdSinglePrecision = 1;
102 mvfr1.advSimdHalfPrecision = 1;
103 mvfr1.vfpHalfPrecision = 1;
104 miscRegs[MISCREG_MVFR1] = mvfr1;
105
105 miscRegs[MISCREG_MPIDR] = 0;
106
107 // Reset values of PRRR and NMRR are implementation dependent
108
109 miscRegs[MISCREG_PRRR] =
110 (1 << 19) | // 19
111 (0 << 18) | // 18
112 (0 << 17) | // 17
113 (1 << 16) | // 16
114 (2 << 14) | // 15:14

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167 misc_reg, flat_idx, val);
168 return val;
169}
170
171
172MiscReg
173ISA::readMiscReg(int misc_reg, ThreadContext *tc)
174{
106 // Reset values of PRRR and NMRR are implementation dependent
107
108 miscRegs[MISCREG_PRRR] =
109 (1 << 19) | // 19
110 (0 << 18) | // 18
111 (0 << 17) | // 17
112 (1 << 16) | // 16
113 (2 << 14) | // 15:14

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166 misc_reg, flat_idx, val);
167 return val;
168}
169
170
171MiscReg
172ISA::readMiscReg(int misc_reg, ThreadContext *tc)
173{
174 ArmSystem *arm_sys;
175
175 if (misc_reg == MISCREG_CPSR) {
176 CPSR cpsr = miscRegs[misc_reg];
177 PCState pc = tc->pcState();
178 cpsr.j = pc.jazelle() ? 1 : 0;
179 cpsr.t = pc.thumb() ? 1 : 0;
180 return cpsr;
181 }
182 if (misc_reg >= MISCREG_CP15_UNIMP_START)
183 panic("Unimplemented CP15 register %s read.\n",
184 miscRegName[misc_reg]);
185
186 switch (misc_reg) {
187 case MISCREG_MPIDR:
176 if (misc_reg == MISCREG_CPSR) {
177 CPSR cpsr = miscRegs[misc_reg];
178 PCState pc = tc->pcState();
179 cpsr.j = pc.jazelle() ? 1 : 0;
180 cpsr.t = pc.thumb() ? 1 : 0;
181 return cpsr;
182 }
183 if (misc_reg >= MISCREG_CP15_UNIMP_START)
184 panic("Unimplemented CP15 register %s read.\n",
185 miscRegName[misc_reg]);
186
187 switch (misc_reg) {
188 case MISCREG_MPIDR:
189 arm_sys = dynamic_cast<ArmSystem*>(tc->getSystemPtr());
190 assert(arm_sys);
188
191
189 return 0x80000000 | // multiprocessor extensions available
190 tc->cpuId();
192 if (arm_sys->multiProc) {
193 return 0x80000000 | // multiprocessor extensions available
194 tc->cpuId();
195 } else {
196 return 0x80000000 | // multiprocessor extensions available
197 0x40000000 | // in up system
198 tc->cpuId();
199 }
191 break;
192 case MISCREG_ID_MMFR0:
193 return 0x03; // VMSAv7 support
194 case MISCREG_ID_MMFR2:
195 return 0x01230000; // no HW access | WFI stalling | ISB and DSB
196 // | all TLB maintenance | no Harvard
197 case MISCREG_ID_MMFR3:
198 return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint |

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201 case MISCREG_ID_MMFR0:
202 return 0x03; // VMSAv7 support
203 case MISCREG_ID_MMFR2:
204 return 0x01230000; // no HW access | WFI stalling | ISB and DSB
205 // | all TLB maintenance | no Harvard
206 case MISCREG_ID_MMFR3:
207 return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint |

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