isa.cc (8873:f349cc840cab) isa.cc (8887:20ea02da9c53)
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "config/use_checker.hh"
42#include "cpu/checker/cpu.hh"
43#include "debug/Arm.hh"
44#include "debug/MiscRegs.hh"
45#include "sim/faults.hh"
46#include "sim/stat_control.hh"
47#include "sim/system.hh"
48
43#include "debug/Arm.hh"
44#include "debug/MiscRegs.hh"
45#include "sim/faults.hh"
46#include "sim/stat_control.hh"
47#include "sim/system.hh"
48
49#if USE_CHECKER
50#include "cpu/checker/cpu.hh"
51#endif
52
53namespace ArmISA
54{
55
56void
57ISA::clear()
58{
59 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
60 uint32_t midr = miscRegs[MISCREG_MIDR];

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289 tc->getDTBPtr()->invalidateMiscReg();
290 }
291
292 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
293 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
294 PCState pc = tc->pcState();
295 pc.nextThumb(cpsr.t);
296 pc.nextJazelle(cpsr.j);
49namespace ArmISA
50{
51
52void
53ISA::clear()
54{
55 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
56 uint32_t midr = miscRegs[MISCREG_MIDR];

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285 tc->getDTBPtr()->invalidateMiscReg();
286 }
287
288 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
289 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
290 PCState pc = tc->pcState();
291 pc.nextThumb(cpsr.t);
292 pc.nextJazelle(cpsr.j);
297#if USE_CHECKER
298 tc->pcStateNoRecord(pc);
299#else
300 tc->pcState(pc);
301#endif //USE_CHECKER
293
294 // Follow slightly different semantics if a CheckerCPU object
295 // is connected
296 CheckerCPU *checker = tc->getCheckerCpuPtr();
297 if (checker) {
298 tc->pcStateNoRecord(pc);
299 } else {
300 tc->pcState(pc);
301 }
302 } else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
303 misc_reg < MISCREG_CP15_END) {
304 panic("Unimplemented CP15 register %s wrote with %#x.\n",
305 miscRegName[misc_reg], val);
306 } else {
307 switch (misc_reg) {
308 case MISCREG_CPACR:
309 {

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396 if (!other_sctlr.c && oc->status() != ThreadContext::Halted)
397 return;
398 }
399
400 for (x = 0; x < sys->numContexts(); x++) {
401 oc = sys->getThreadContext(x);
402 oc->getDTBPtr()->allCpusCaching();
403 oc->getITBPtr()->allCpusCaching();
302 } else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
303 misc_reg < MISCREG_CP15_END) {
304 panic("Unimplemented CP15 register %s wrote with %#x.\n",
305 miscRegName[misc_reg], val);
306 } else {
307 switch (misc_reg) {
308 case MISCREG_CPACR:
309 {

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396 if (!other_sctlr.c && oc->status() != ThreadContext::Halted)
397 return;
398 }
399
400 for (x = 0; x < sys->numContexts(); x++) {
401 oc = sys->getThreadContext(x);
402 oc->getDTBPtr()->allCpusCaching();
403 oc->getITBPtr()->allCpusCaching();
404#if USE_CHECKER
405 CheckerCPU *checker =
406 dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
404
405 // If CheckerCPU is connected, need to notify it.
406 CheckerCPU *checker = oc->getCheckerCpuPtr();
407 if (checker) {
408 checker->getDTBPtr()->allCpusCaching();
409 checker->getITBPtr()->allCpusCaching();
410 }
407 if (checker) {
408 checker->getDTBPtr()->allCpusCaching();
409 checker->getITBPtr()->allCpusCaching();
410 }
411#endif
412 }
413 return;
414 }
415 case MISCREG_TLBTR:
416 case MISCREG_MVFR0:
417 case MISCREG_MVFR1:
418 case MISCREG_MPIDR:
419 case MISCREG_FPSID:
420 return;
421 case MISCREG_TLBIALLIS:
422 case MISCREG_TLBIALL:
423 sys = tc->getSystemPtr();
424 for (x = 0; x < sys->numContexts(); x++) {
425 oc = sys->getThreadContext(x);
426 assert(oc->getITBPtr() && oc->getDTBPtr());
427 oc->getITBPtr()->flushAll();
428 oc->getDTBPtr()->flushAll();
411 }
412 return;
413 }
414 case MISCREG_TLBTR:
415 case MISCREG_MVFR0:
416 case MISCREG_MVFR1:
417 case MISCREG_MPIDR:
418 case MISCREG_FPSID:
419 return;
420 case MISCREG_TLBIALLIS:
421 case MISCREG_TLBIALL:
422 sys = tc->getSystemPtr();
423 for (x = 0; x < sys->numContexts(); x++) {
424 oc = sys->getThreadContext(x);
425 assert(oc->getITBPtr() && oc->getDTBPtr());
426 oc->getITBPtr()->flushAll();
427 oc->getDTBPtr()->flushAll();
429#if USE_CHECKER
430 CheckerCPU *checker =
431 dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
428
429 // If CheckerCPU is connected, need to notify it of a flush
430 CheckerCPU *checker = oc->getCheckerCpuPtr();
432 if (checker) {
433 checker->getITBPtr()->flushAll();
434 checker->getDTBPtr()->flushAll();
435 }
431 if (checker) {
432 checker->getITBPtr()->flushAll();
433 checker->getDTBPtr()->flushAll();
434 }
436#endif
437 }
438 return;
439 case MISCREG_ITLBIALL:
440 tc->getITBPtr()->flushAll();
441 return;
442 case MISCREG_DTLBIALL:
443 tc->getDTBPtr()->flushAll();
444 return;
445 case MISCREG_TLBIMVAIS:
446 case MISCREG_TLBIMVA:
447 sys = tc->getSystemPtr();
448 for (x = 0; x < sys->numContexts(); x++) {
449 oc = sys->getThreadContext(x);
450 assert(oc->getITBPtr() && oc->getDTBPtr());
451 oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
452 bits(newVal, 7,0));
453 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
454 bits(newVal, 7,0));
435 }
436 return;
437 case MISCREG_ITLBIALL:
438 tc->getITBPtr()->flushAll();
439 return;
440 case MISCREG_DTLBIALL:
441 tc->getDTBPtr()->flushAll();
442 return;
443 case MISCREG_TLBIMVAIS:
444 case MISCREG_TLBIMVA:
445 sys = tc->getSystemPtr();
446 for (x = 0; x < sys->numContexts(); x++) {
447 oc = sys->getThreadContext(x);
448 assert(oc->getITBPtr() && oc->getDTBPtr());
449 oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
450 bits(newVal, 7,0));
451 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
452 bits(newVal, 7,0));
455#if USE_CHECKER
456 CheckerCPU *checker =
457 dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
453
454 CheckerCPU *checker = oc->getCheckerCpuPtr();
458 if (checker) {
459 checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
460 bits(newVal, 7,0));
461 checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
462 bits(newVal, 7,0));
463 }
455 if (checker) {
456 checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
457 bits(newVal, 7,0));
458 checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
459 bits(newVal, 7,0));
460 }
464#endif
465 }
466 return;
467 case MISCREG_TLBIASIDIS:
468 case MISCREG_TLBIASID:
469 sys = tc->getSystemPtr();
470 for (x = 0; x < sys->numContexts(); x++) {
471 oc = sys->getThreadContext(x);
472 assert(oc->getITBPtr() && oc->getDTBPtr());
473 oc->getITBPtr()->flushAsid(bits(newVal, 7,0));
474 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
461 }
462 return;
463 case MISCREG_TLBIASIDIS:
464 case MISCREG_TLBIASID:
465 sys = tc->getSystemPtr();
466 for (x = 0; x < sys->numContexts(); x++) {
467 oc = sys->getThreadContext(x);
468 assert(oc->getITBPtr() && oc->getDTBPtr());
469 oc->getITBPtr()->flushAsid(bits(newVal, 7,0));
470 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
475#if USE_CHECKER
476 CheckerCPU *checker =
477 dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
471 CheckerCPU *checker = oc->getCheckerCpuPtr();
478 if (checker) {
479 checker->getITBPtr()->flushAsid(bits(newVal, 7,0));
480 checker->getDTBPtr()->flushAsid(bits(newVal, 7,0));
481 }
472 if (checker) {
473 checker->getITBPtr()->flushAsid(bits(newVal, 7,0));
474 checker->getDTBPtr()->flushAsid(bits(newVal, 7,0));
475 }
482#endif
483 }
484 return;
485 case MISCREG_TLBIMVAAIS:
486 case MISCREG_TLBIMVAA:
487 sys = tc->getSystemPtr();
488 for (x = 0; x < sys->numContexts(); x++) {
489 oc = sys->getThreadContext(x);
490 assert(oc->getITBPtr() && oc->getDTBPtr());
491 oc->getITBPtr()->flushMva(mbits(newVal, 31,12));
492 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
476 }
477 return;
478 case MISCREG_TLBIMVAAIS:
479 case MISCREG_TLBIMVAA:
480 sys = tc->getSystemPtr();
481 for (x = 0; x < sys->numContexts(); x++) {
482 oc = sys->getThreadContext(x);
483 assert(oc->getITBPtr() && oc->getDTBPtr());
484 oc->getITBPtr()->flushMva(mbits(newVal, 31,12));
485 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
493#if USE_CHECKER
494 CheckerCPU *checker =
495 dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
486
487 CheckerCPU *checker = oc->getCheckerCpuPtr();
496 if (checker) {
497 checker->getITBPtr()->flushMva(mbits(newVal, 31,12));
498 checker->getDTBPtr()->flushMva(mbits(newVal, 31,12));
499 }
488 if (checker) {
489 checker->getITBPtr()->flushMva(mbits(newVal, 31,12));
490 checker->getDTBPtr()->flushMva(mbits(newVal, 31,12));
491 }
500#endif
501 }
502 return;
503 case MISCREG_ITLBIMVA:
504 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
505 bits(newVal, 7,0));
506 return;
507 case MISCREG_DTLBIMVA:
508 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),

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493 return;
494 case MISCREG_ITLBIMVA:
495 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
496 bits(newVal, 7,0));
497 return;
498 case MISCREG_DTLBIMVA:
499 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),

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