isa.cc (8832:247fee427324) isa.cc (8868:26dbd171754e)
1/*
1/*
2 * Copyright (c) 2010-2011 ARM Limited
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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228 break;
229 case MISCREG_CPSR_Q:
230 panic("shouldn't be reading this register seperately\n");
231 case MISCREG_FPSCR_QC:
232 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
233 case MISCREG_FPSCR_EXC:
234 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
235 case MISCREG_L2CTLR:
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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228 break;
229 case MISCREG_CPSR_Q:
230 panic("shouldn't be reading this register seperately\n");
231 case MISCREG_FPSCR_QC:
232 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
233 case MISCREG_FPSCR_EXC:
234 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
235 case MISCREG_L2CTLR:
236 // mostly unimplemented, just set NumCPUs field from sim and return
237 L2CTLR l2ctlr = 0;
238 // b00:1CPU to b11:4CPUs
239 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
240 return l2ctlr;
236 {
237 // mostly unimplemented, just set NumCPUs field from sim and return
238 L2CTLR l2ctlr = 0;
239 // b00:1CPU to b11:4CPUs
240 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
241 return l2ctlr;
242 }
243 case MISCREG_DBGDIDR:
244 /* For now just implement the version number.
245 * Return 0 as we don't support debug architecture yet.
246 */
247 return 0;
248 case MISCREG_DBGDSCR_INT:
249 return 0;
241 }
242 return readMiscRegNoEffect(misc_reg);
243}
244
245void
246ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
247{
248 assert(misc_reg < NumMiscRegs);

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251 return readMiscRegNoEffect(misc_reg);
252}
253
254void
255ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
256{
257 assert(misc_reg < NumMiscRegs);

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