isa.cc (8549:7cff2156c998) isa.cc (8733:64a7bf8fa56c)
1/*
1/*
2 * Copyright (c) 2010 ARM Limited
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "config/use_checker.hh"
42#include "debug/Arm.hh"
43#include "debug/MiscRegs.hh"
44#include "sim/faults.hh"
45#include "sim/stat_control.hh"
46#include "sim/system.hh"
47
43#include "debug/Arm.hh"
44#include "debug/MiscRegs.hh"
45#include "sim/faults.hh"
46#include "sim/stat_control.hh"
47#include "sim/system.hh"
48
49#if USE_CHECKER
50#include "cpu/checker/cpu.hh"
51#endif
52
48namespace ArmISA
49{
50
51void
52ISA::clear()
53{
54 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
55 uint32_t midr = miscRegs[MISCREG_MIDR];

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274 tc->getDTBPtr()->invalidateMiscReg();
275 }
276
277 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
278 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
279 PCState pc = tc->pcState();
280 pc.nextThumb(cpsr.t);
281 pc.nextJazelle(cpsr.j);
53namespace ArmISA
54{
55
56void
57ISA::clear()
58{
59 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
60 uint32_t midr = miscRegs[MISCREG_MIDR];

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279 tc->getDTBPtr()->invalidateMiscReg();
280 }
281
282 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
283 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
284 PCState pc = tc->pcState();
285 pc.nextThumb(cpsr.t);
286 pc.nextJazelle(cpsr.j);
287#if USE_CHECKER
288 tc->pcStateNoRecord(pc);
289#else
282 tc->pcState(pc);
290 tc->pcState(pc);
291#endif //USE_CHECKER
283 } else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
284 misc_reg < MISCREG_CP15_END) {
285 panic("Unimplemented CP15 register %s wrote with %#x.\n",
286 miscRegName[misc_reg], val);
287 } else {
288 switch (misc_reg) {
289 case MISCREG_CPACR:
290 {

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377 if (!other_sctlr.c && oc->status() != ThreadContext::Halted)
378 return;
379 }
380
381 for (x = 0; x < sys->numContexts(); x++) {
382 oc = sys->getThreadContext(x);
383 oc->getDTBPtr()->allCpusCaching();
384 oc->getITBPtr()->allCpusCaching();
292 } else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
293 misc_reg < MISCREG_CP15_END) {
294 panic("Unimplemented CP15 register %s wrote with %#x.\n",
295 miscRegName[misc_reg], val);
296 } else {
297 switch (misc_reg) {
298 case MISCREG_CPACR:
299 {

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386 if (!other_sctlr.c && oc->status() != ThreadContext::Halted)
387 return;
388 }
389
390 for (x = 0; x < sys->numContexts(); x++) {
391 oc = sys->getThreadContext(x);
392 oc->getDTBPtr()->allCpusCaching();
393 oc->getITBPtr()->allCpusCaching();
394#if USE_CHECKER
395 CheckerCPU *checker =
396 dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
397 if (checker) {
398 checker->getDTBPtr()->allCpusCaching();
399 checker->getITBPtr()->allCpusCaching();
400 }
401#endif
385 }
386 return;
387 }
388 case MISCREG_TLBTR:
389 case MISCREG_MVFR0:
390 case MISCREG_MVFR1:
391 case MISCREG_MPIDR:
392 case MISCREG_FPSID:
393 return;
394 case MISCREG_TLBIALLIS:
395 case MISCREG_TLBIALL:
396 sys = tc->getSystemPtr();
397 for (x = 0; x < sys->numContexts(); x++) {
398 oc = sys->getThreadContext(x);
399 assert(oc->getITBPtr() && oc->getDTBPtr());
400 oc->getITBPtr()->flushAll();
401 oc->getDTBPtr()->flushAll();
402 }
403 return;
404 }
405 case MISCREG_TLBTR:
406 case MISCREG_MVFR0:
407 case MISCREG_MVFR1:
408 case MISCREG_MPIDR:
409 case MISCREG_FPSID:
410 return;
411 case MISCREG_TLBIALLIS:
412 case MISCREG_TLBIALL:
413 sys = tc->getSystemPtr();
414 for (x = 0; x < sys->numContexts(); x++) {
415 oc = sys->getThreadContext(x);
416 assert(oc->getITBPtr() && oc->getDTBPtr());
417 oc->getITBPtr()->flushAll();
418 oc->getDTBPtr()->flushAll();
419#if USE_CHECKER
420 CheckerCPU *checker =
421 dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
422 if (checker) {
423 checker->getITBPtr()->flushAll();
424 checker->getDTBPtr()->flushAll();
425 }
426#endif
402 }
403 return;
404 case MISCREG_ITLBIALL:
405 tc->getITBPtr()->flushAll();
406 return;
407 case MISCREG_DTLBIALL:
408 tc->getDTBPtr()->flushAll();
409 return;
410 case MISCREG_TLBIMVAIS:
411 case MISCREG_TLBIMVA:
412 sys = tc->getSystemPtr();
413 for (x = 0; x < sys->numContexts(); x++) {
414 oc = sys->getThreadContext(x);
415 assert(oc->getITBPtr() && oc->getDTBPtr());
416 oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
417 bits(newVal, 7,0));
418 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
419 bits(newVal, 7,0));
427 }
428 return;
429 case MISCREG_ITLBIALL:
430 tc->getITBPtr()->flushAll();
431 return;
432 case MISCREG_DTLBIALL:
433 tc->getDTBPtr()->flushAll();
434 return;
435 case MISCREG_TLBIMVAIS:
436 case MISCREG_TLBIMVA:
437 sys = tc->getSystemPtr();
438 for (x = 0; x < sys->numContexts(); x++) {
439 oc = sys->getThreadContext(x);
440 assert(oc->getITBPtr() && oc->getDTBPtr());
441 oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
442 bits(newVal, 7,0));
443 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
444 bits(newVal, 7,0));
445#if USE_CHECKER
446 CheckerCPU *checker =
447 dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
448 if (checker) {
449 checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
450 bits(newVal, 7,0));
451 checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
452 bits(newVal, 7,0));
453 }
454#endif
420 }
421 return;
422 case MISCREG_TLBIASIDIS:
423 case MISCREG_TLBIASID:
424 sys = tc->getSystemPtr();
425 for (x = 0; x < sys->numContexts(); x++) {
426 oc = sys->getThreadContext(x);
427 assert(oc->getITBPtr() && oc->getDTBPtr());
428 oc->getITBPtr()->flushAsid(bits(newVal, 7,0));
429 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
455 }
456 return;
457 case MISCREG_TLBIASIDIS:
458 case MISCREG_TLBIASID:
459 sys = tc->getSystemPtr();
460 for (x = 0; x < sys->numContexts(); x++) {
461 oc = sys->getThreadContext(x);
462 assert(oc->getITBPtr() && oc->getDTBPtr());
463 oc->getITBPtr()->flushAsid(bits(newVal, 7,0));
464 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
465#if USE_CHECKER
466 CheckerCPU *checker =
467 dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
468 if (checker) {
469 checker->getITBPtr()->flushAsid(bits(newVal, 7,0));
470 checker->getDTBPtr()->flushAsid(bits(newVal, 7,0));
471 }
472#endif
430 }
431 return;
432 case MISCREG_TLBIMVAAIS:
433 case MISCREG_TLBIMVAA:
434 sys = tc->getSystemPtr();
435 for (x = 0; x < sys->numContexts(); x++) {
436 oc = sys->getThreadContext(x);
437 assert(oc->getITBPtr() && oc->getDTBPtr());
438 oc->getITBPtr()->flushMva(mbits(newVal, 31,12));
439 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
473 }
474 return;
475 case MISCREG_TLBIMVAAIS:
476 case MISCREG_TLBIMVAA:
477 sys = tc->getSystemPtr();
478 for (x = 0; x < sys->numContexts(); x++) {
479 oc = sys->getThreadContext(x);
480 assert(oc->getITBPtr() && oc->getDTBPtr());
481 oc->getITBPtr()->flushMva(mbits(newVal, 31,12));
482 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
483#if USE_CHECKER
484 CheckerCPU *checker =
485 dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
486 if (checker) {
487 checker->getITBPtr()->flushMva(mbits(newVal, 31,12));
488 checker->getDTBPtr()->flushMva(mbits(newVal, 31,12));
489 }
490#endif
440 }
441 return;
442 case MISCREG_ITLBIMVA:
443 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
444 bits(newVal, 7,0));
445 return;
446 case MISCREG_DTLBIMVA:
447 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),

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492 return;
493 case MISCREG_ITLBIMVA:
494 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
495 bits(newVal, 7,0));
496 return;
497 case MISCREG_DTLBIMVA:
498 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),

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