isa.cc (8527:6bac5b04d588) isa.cc (8549:7cff2156c998)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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222 miscRegName[misc_reg]);
223 break;
224 case MISCREG_CPSR_Q:
225 panic("shouldn't be reading this register seperately\n");
226 case MISCREG_FPSCR_QC:
227 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
228 case MISCREG_FPSCR_EXC:
229 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 213 unchanged lines hidden (view full) ---

222 miscRegName[misc_reg]);
223 break;
224 case MISCREG_CPSR_Q:
225 panic("shouldn't be reading this register seperately\n");
226 case MISCREG_FPSCR_QC:
227 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
228 case MISCREG_FPSCR_EXC:
229 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
230 case MISCREG_L2CTLR:
231 // mostly unimplemented, just set NumCPUs field from sim and return
232 L2CTLR l2ctlr = 0;
233 // b00:1CPU to b11:4CPUs
234 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
235 return l2ctlr;
230 }
231 return readMiscRegNoEffect(misc_reg);
232}
233
234void
235ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
236{
237 assert(misc_reg < NumMiscRegs);

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532 break;
533 case MISCREG_CPSR_MODE:
534 // This miscreg is used by copy*Regs to set the CPSR mode
535 // without updating other CPSR variables. It's used to
536 // make sure the register map is in such a state that we can
537 // see all of the registers for the copy.
538 updateRegMap(val);
539 return;
236 }
237 return readMiscRegNoEffect(misc_reg);
238}
239
240void
241ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
242{
243 assert(misc_reg < NumMiscRegs);

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538 break;
539 case MISCREG_CPSR_MODE:
540 // This miscreg is used by copy*Regs to set the CPSR mode
541 // without updating other CPSR variables. It's used to
542 // make sure the register map is in such a state that we can
543 // see all of the registers for the copy.
544 updateRegMap(val);
545 return;
546 case MISCREG_L2CTLR:
547 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
548 miscRegName[misc_reg], uint32_t(val));
540 }
541 }
542 setMiscRegNoEffect(misc_reg, newVal);
543}
544
545}
549 }
550 }
551 setMiscRegNoEffect(misc_reg, newVal);
552}
553
554}