isa.cc (8302:9f23d01421de) isa.cc (8468:5e9530779f60)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 172 unchanged lines hidden (view full) ---

181 if (misc_reg >= MISCREG_CP15_UNIMP_START)
182 panic("Unimplemented CP15 register %s read.\n",
183 miscRegName[misc_reg]);
184
185 switch (misc_reg) {
186 case MISCREG_MPIDR:
187 return tc->cpuId();
188 break;
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 172 unchanged lines hidden (view full) ---

181 if (misc_reg >= MISCREG_CP15_UNIMP_START)
182 panic("Unimplemented CP15 register %s read.\n",
183 miscRegName[misc_reg]);
184
185 switch (misc_reg) {
186 case MISCREG_MPIDR:
187 return tc->cpuId();
188 break;
189 case MISCREG_ID_MMFR0:
190 return 0x03; // VMSAv7 support
191 case MISCREG_ID_MMFR2:
192 return 0x01230000; // no HW access | WFI stalling | ISB and DSB
193 // | all TLB maintenance | no Harvard
189 case MISCREG_ID_MMFR3:
190 return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint |
191 // BP Maint | Cache Maint Set/way | Cache Maint MVA
192 case MISCREG_CLIDR:
193 warn_once("The clidr register always reports 0 caches.\n");
194 case MISCREG_ID_MMFR3:
195 return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint |
196 // BP Maint | Cache Maint Set/way | Cache Maint MVA
197 case MISCREG_CLIDR:
198 warn_once("The clidr register always reports 0 caches.\n");
194 break;
199 warn_once("clidr LoUIS field of 0b001 to match current "
200 "ARM implementations.\n");
201 return 0x00200000;
195 case MISCREG_CCSIDR:
196 warn_once("The ccsidr register isn't implemented and "
197 "always reads as 0.\n");
198 break;
199 case MISCREG_ID_PFR0:
200 warn("Returning thumbEE disabled for now since we don't support CP14"
201 "config registers and jumping to ThumbEE vectors\n");
202 return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM
203 case MISCREG_ID_PFR1:
204 warn("reading unimplmented register ID_PFR1");
205 return 0;
202 case MISCREG_CCSIDR:
203 warn_once("The ccsidr register isn't implemented and "
204 "always reads as 0.\n");
205 break;
206 case MISCREG_ID_PFR0:
207 warn("Returning thumbEE disabled for now since we don't support CP14"
208 "config registers and jumping to ThumbEE vectors\n");
209 return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM
210 case MISCREG_ID_PFR1:
211 warn("reading unimplmented register ID_PFR1");
212 return 0;
206 case MISCREG_ID_MMFR0:
207 return 0x03; //VMSAz7
208 case MISCREG_CTR:
209 return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact
210 case MISCREG_ACTLR:
211 warn("Not doing anything for miscreg ACTLR\n");
212 break;
213 case MISCREG_PMCR:
214 case MISCREG_PMCCNTR:
215 case MISCREG_PMSELR:

--- 308 unchanged lines hidden --- 		213 case MISCREG_CTR:
214 return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact
215 case MISCREG_ACTLR:
216 warn("Not doing anything for miscreg ACTLR\n");
217 break;
218 case MISCREG_PMCR:
219 case MISCREG_PMCCNTR:
220 case MISCREG_PMSELR:

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