isa.cc (8284:2fcad6253525) isa.cc (8299:64a938a8b7fc)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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47
48namespace ArmISA
49{
50
51void
52ISA::clear()
53{
54 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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47
48namespace ArmISA
49{
50
51void
52ISA::clear()
53{
54 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
55
55 uint32_t midr = miscRegs[MISCREG_MIDR];
56 memset(miscRegs, 0, sizeof(miscRegs));
57 CPSR cpsr = 0;
58 cpsr.mode = MODE_USER;
59 miscRegs[MISCREG_CPSR] = cpsr;
60 updateRegMap(cpsr);
61
62 SCTLR sctlr = 0;
63 sctlr.te = (bool)sctlr_rst.te;
64 sctlr.nmfi = (bool)sctlr_rst.nmfi;
65 sctlr.v = (bool)sctlr_rst.v;
66 sctlr.u = 1;
67 sctlr.xp = 1;
68 sctlr.rao2 = 1;
69 sctlr.rao3 = 1;
70 sctlr.rao4 = 1;
71 miscRegs[MISCREG_SCTLR] = sctlr;
72 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
73
56 memset(miscRegs, 0, sizeof(miscRegs));
57 CPSR cpsr = 0;
58 cpsr.mode = MODE_USER;
59 miscRegs[MISCREG_CPSR] = cpsr;
60 updateRegMap(cpsr);
61
62 SCTLR sctlr = 0;
63 sctlr.te = (bool)sctlr_rst.te;
64 sctlr.nmfi = (bool)sctlr_rst.nmfi;
65 sctlr.v = (bool)sctlr_rst.v;
66 sctlr.u = 1;
67 sctlr.xp = 1;
68 sctlr.rao2 = 1;
69 sctlr.rao3 = 1;
70 sctlr.rao4 = 1;
71 miscRegs[MISCREG_SCTLR] = sctlr;
72 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
73
74 // Preserve MIDR accross reset
75 miscRegs[MISCREG_MIDR] = midr;
76
74 /* Start with an event in the mailbox */
75 miscRegs[MISCREG_SEV_MAILBOX] = 1;
76
77 /* Start with an event in the mailbox */
78 miscRegs[MISCREG_SEV_MAILBOX] = 1;
79
77 /*
78 * Implemented = '5' from "M5",
79 * Variant = 0,
80 */
81 miscRegs[MISCREG_MIDR] =
82 (0x35 << 24) | // Implementor is '5' from "M5"
83 (0 << 20) | // Variant
84 (0xf << 16) | // Architecture from CPUID scheme
85 (0xf00 << 4) | // Primary part number
86 (0 << 0) | // Revision
87 0;
88
89 // Separate Instruction and Data TLBs.
90 miscRegs[MISCREG_TLBTR] = 1;
91
92 MVFR0 mvfr0 = 0;
93 mvfr0.advSimdRegisters = 2;
94 mvfr0.singlePrecision = 2;
95 mvfr0.doublePrecision = 2;
96 mvfr0.vfpExceptionTrapping = 0;

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204 case MISCREG_CCSIDR:
205 warn_once("The ccsidr register isn't implemented and "
206 "always reads as 0.\n");
207 break;
208 case MISCREG_ID_PFR0:
209 warn("Returning thumbEE disabled for now since we don't support CP14"
210 "config registers and jumping to ThumbEE vectors\n");
211 return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM
80 // Separate Instruction and Data TLBs.
81 miscRegs[MISCREG_TLBTR] = 1;
82
83 MVFR0 mvfr0 = 0;
84 mvfr0.advSimdRegisters = 2;
85 mvfr0.singlePrecision = 2;
86 mvfr0.doublePrecision = 2;
87 mvfr0.vfpExceptionTrapping = 0;

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195 case MISCREG_CCSIDR:
196 warn_once("The ccsidr register isn't implemented and "
197 "always reads as 0.\n");
198 break;
199 case MISCREG_ID_PFR0:
200 warn("Returning thumbEE disabled for now since we don't support CP14"
201 "config registers and jumping to ThumbEE vectors\n");
202 return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM
203 case MISCREG_ID_PFR1:
204 warn("reading unimplmented register ID_PFR1");
205 return 0;
212 case MISCREG_ID_MMFR0:
213 return 0x03; //VMSAz7
214 case MISCREG_CTR:
215 return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact
216 case MISCREG_ACTLR:
217 warn("Not doing anything for miscreg ACTLR\n");
218 break;
219 case MISCREG_PMCR:
220 case MISCREG_PMCCNTR:
221 case MISCREG_PMSELR:
206 case MISCREG_ID_MMFR0:
207 return 0x03; //VMSAz7
208 case MISCREG_CTR:
209 return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact
210 case MISCREG_ACTLR:
211 warn("Not doing anything for miscreg ACTLR\n");
212 break;
213 case MISCREG_PMCR:
214 case MISCREG_PMCCNTR:
215 case MISCREG_PMSELR:
222 warn("Not doing anyhting for read to miscreg %s\n",
216 warn("Not doing anything for read to miscreg %s\n",
223 miscRegName[misc_reg]);
224 break;
225 case MISCREG_FPSCR_QC:
226 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
227 case MISCREG_FPSCR_EXC:
228 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
229 }
230 return readMiscRegNoEffect(misc_reg);

--- 290 unchanged lines hidden --- 		217 miscRegName[misc_reg]);
218 break;
219 case MISCREG_FPSCR_QC:
220 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
221 case MISCREG_FPSCR_EXC:
222 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
223 }
224 return readMiscRegNoEffect(misc_reg);

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