isa.cc (8232:b28d06a175be) isa.cc (8284:2fcad6253525)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "debug/Arm.hh"
43#include "debug/MiscRegs.hh"
44#include "sim/faults.hh"
45#include "sim/stat_control.hh"
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "debug/Arm.hh"
43#include "debug/MiscRegs.hh"
44#include "sim/faults.hh"
45#include "sim/stat_control.hh"
46#include "sim/system.hh"
46
47namespace ArmISA
48{
49
50void
51ISA::clear()
52{
53 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];

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186 cpsr.t = pc.thumb() ? 1 : 0;
187 return cpsr;
188 }
189 if (misc_reg >= MISCREG_CP15_UNIMP_START)
190 panic("Unimplemented CP15 register %s read.\n",
191 miscRegName[misc_reg]);
192
193 switch (misc_reg) {
47
48namespace ArmISA
49{
50
51void
52ISA::clear()
53{
54 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];

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187 cpsr.t = pc.thumb() ? 1 : 0;
188 return cpsr;
189 }
190 if (misc_reg >= MISCREG_CP15_UNIMP_START)
191 panic("Unimplemented CP15 register %s read.\n",
192 miscRegName[misc_reg]);
193
194 switch (misc_reg) {
195 case MISCREG_MPIDR:
196 return tc->cpuId();
197 break;
198 case MISCREG_ID_MMFR3:
199 return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint |
200 // BP Maint | Cache Maint Set/way | Cache Maint MVA
194 case MISCREG_CLIDR:
195 warn_once("The clidr register always reports 0 caches.\n");
196 break;
197 case MISCREG_CCSIDR:
198 warn_once("The ccsidr register isn't implemented and "
199 "always reads as 0.\n");
200 break;
201 case MISCREG_ID_PFR0:

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239 flat_idx, val);
240}
241
242void
243ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
244{
245
246 MiscReg newVal = val;
201 case MISCREG_CLIDR:
202 warn_once("The clidr register always reports 0 caches.\n");
203 break;
204 case MISCREG_CCSIDR:
205 warn_once("The ccsidr register isn't implemented and "
206 "always reads as 0.\n");
207 break;
208 case MISCREG_ID_PFR0:

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246 flat_idx, val);
247}
248
249void
250ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
251{
252
253 MiscReg newVal = val;
254 int x;
255 System *sys;
256 ThreadContext *oc;
257
247 if (misc_reg == MISCREG_CPSR) {
248 updateRegMap(val);
249
250
251 CPSR old_cpsr = miscRegs[MISCREG_CPSR];
252 int old_mode = old_cpsr.mode;
253 CPSR cpsr = val;
254 if (old_mode != cpsr.mode) {

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346 case MISCREG_TLBTR:
347 case MISCREG_MVFR0:
348 case MISCREG_MVFR1:
349 case MISCREG_MPIDR:
350 case MISCREG_FPSID:
351 return;
352 case MISCREG_TLBIALLIS:
353 case MISCREG_TLBIALL:
258 if (misc_reg == MISCREG_CPSR) {
259 updateRegMap(val);
260
261
262 CPSR old_cpsr = miscRegs[MISCREG_CPSR];
263 int old_mode = old_cpsr.mode;
264 CPSR cpsr = val;
265 if (old_mode != cpsr.mode) {

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357 case MISCREG_TLBTR:
358 case MISCREG_MVFR0:
359 case MISCREG_MVFR1:
360 case MISCREG_MPIDR:
361 case MISCREG_FPSID:
362 return;
363 case MISCREG_TLBIALLIS:
364 case MISCREG_TLBIALL:
354 warn_once("Need to flush all TLBs in MP\n");
355 tc->getITBPtr()->flushAll();
356 tc->getDTBPtr()->flushAll();
365 sys = tc->getSystemPtr();
366 for (x = 0; x < sys->numContexts(); x++) {
367 oc = sys->getThreadContext(x);
368 assert(oc->getITBPtr() && oc->getDTBPtr());
369 oc->getITBPtr()->flushAll();
370 oc->getDTBPtr()->flushAll();
371 }
357 return;
358 case MISCREG_ITLBIALL:
359 tc->getITBPtr()->flushAll();
360 return;
361 case MISCREG_DTLBIALL:
362 tc->getDTBPtr()->flushAll();
363 return;
364 case MISCREG_TLBIMVAIS:
365 case MISCREG_TLBIMVA:
372 return;
373 case MISCREG_ITLBIALL:
374 tc->getITBPtr()->flushAll();
375 return;
376 case MISCREG_DTLBIALL:
377 tc->getDTBPtr()->flushAll();
378 return;
379 case MISCREG_TLBIMVAIS:
380 case MISCREG_TLBIMVA:
366 warn_once("Need to flush all TLBs in MP\n");
367 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
368 bits(newVal, 7,0));
369 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
370 bits(newVal, 7,0));
381 sys = tc->getSystemPtr();
382 for (x = 0; x < sys->numContexts(); x++) {
383 oc = sys->getThreadContext(x);
384 assert(oc->getITBPtr() && oc->getDTBPtr());
385 oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
386 bits(newVal, 7,0));
387 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
388 bits(newVal, 7,0));
389 }
371 return;
372 case MISCREG_TLBIASIDIS:
373 case MISCREG_TLBIASID:
390 return;
391 case MISCREG_TLBIASIDIS:
392 case MISCREG_TLBIASID:
374 warn_once("Need to flush all TLBs in MP\n");
375 tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
376 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
393 sys = tc->getSystemPtr();
394 for (x = 0; x < sys->numContexts(); x++) {
395 oc = sys->getThreadContext(x);
396 assert(oc->getITBPtr() && oc->getDTBPtr());
397 oc->getITBPtr()->flushAsid(bits(newVal, 7,0));
398 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
399 }
377 return;
378 case MISCREG_TLBIMVAAIS:
379 case MISCREG_TLBIMVAA:
400 return;
401 case MISCREG_TLBIMVAAIS:
402 case MISCREG_TLBIMVAA:
380 warn_once("Need to flush all TLBs in MP\n");
381 tc->getITBPtr()->flushMva(mbits(newVal, 31,12));
382 tc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
403 sys = tc->getSystemPtr();
404 for (x = 0; x < sys->numContexts(); x++) {
405 oc = sys->getThreadContext(x);
406 assert(oc->getITBPtr() && oc->getDTBPtr());
407 oc->getITBPtr()->flushMva(mbits(newVal, 31,12));
408 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
409 }
383 return;
384 case MISCREG_ITLBIMVA:
385 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
386 bits(newVal, 7,0));
387 return;
388 case MISCREG_DTLBIMVA:
389 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
390 bits(newVal, 7,0));

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411 case MISCREG_ITLBIMVA:
412 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
413 bits(newVal, 7,0));
414 return;
415 case MISCREG_DTLBIMVA:
416 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
417 bits(newVal, 7,0));

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