isa.cc (7757:d7360f5052b2) isa.cc (7783:9b880b40ac10)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 188 unchanged lines hidden (view full) ---

197 warn("Not doing anything for miscreg ACTLR\n");
198 break;
199 case MISCREG_PMCR:
200 case MISCREG_PMCCNTR:
201 case MISCREG_PMSELR:
202 warn("Not doing anyhting for read to miscreg %s\n",
203 miscRegName[misc_reg]);
204 break;
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 188 unchanged lines hidden (view full) ---

197 warn("Not doing anything for miscreg ACTLR\n");
198 break;
199 case MISCREG_PMCR:
200 case MISCREG_PMCCNTR:
201 case MISCREG_PMSELR:
202 warn("Not doing anyhting for read to miscreg %s\n",
203 miscRegName[misc_reg]);
204 break;
205
205 case MISCREG_FPSCR_QC:
206 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
207 case MISCREG_FPSCR_EXC:
208 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
206 }
207 return readMiscRegNoEffect(misc_reg);
208}
209
210void
211ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
212{
213 assert(misc_reg < NumMiscRegs);

--- 85 unchanged lines hidden (view full) ---

299 fpscrMask.v = ones;
300 fpscrMask.c = ones;
301 fpscrMask.z = ones;
302 fpscrMask.n = ones;
303 newVal = (newVal & (uint32_t)fpscrMask) |
304 (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
305 }
306 break;
209 }
210 return readMiscRegNoEffect(misc_reg);
211}
212
213void
214ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
215{
216 assert(misc_reg < NumMiscRegs);

--- 85 unchanged lines hidden (view full) ---

302 fpscrMask.v = ones;
303 fpscrMask.c = ones;
304 fpscrMask.z = ones;
305 fpscrMask.n = ones;
306 newVal = (newVal & (uint32_t)fpscrMask) |
307 (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
308 }
309 break;
310 case MISCREG_FPSCR_QC:
311 {
312 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask);
313 misc_reg = MISCREG_FPSCR;
314 }
315 break;
316 case MISCREG_FPSCR_EXC:
317 {
318 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask);
319 misc_reg = MISCREG_FPSCR;
320 }
321 break;
307 case MISCREG_FPEXC:
308 {
309 const uint32_t fpexcMask = 0x60000000;
310 newVal = (newVal & fpexcMask) |
311 (miscRegs[MISCREG_FPEXC] & ~fpexcMask);
312 }
313 break;
314 case MISCREG_SCTLR:

--- 139 unchanged lines hidden --- 		322 case MISCREG_FPEXC:
323 {
324 const uint32_t fpexcMask = 0x60000000;
325 newVal = (newVal & fpexcMask) |
326 (miscRegs[MISCREG_FPEXC] & ~fpexcMask);
327 }
328 break;
329 case MISCREG_SCTLR:

--- 139 unchanged lines hidden ---