isa.cc (7731:e1eace3a118a) | isa.cc (7749:859e8bc1cdc2) |
---|---|
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 213 unchanged lines hidden (view full) --- 222 223 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg, 224 flat_idx, val); 225} 226 227void 228ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 229{ | 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 213 unchanged lines hidden (view full) --- 222 223 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg, 224 flat_idx, val); 225} 226 227void 228ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 229{ |
230 |
|
230 MiscReg newVal = val; 231 if (misc_reg == MISCREG_CPSR) { 232 updateRegMap(val); | 231 MiscReg newVal = val; 232 if (misc_reg == MISCREG_CPSR) { 233 updateRegMap(val); |
234 235 236 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 237 int old_mode = old_cpsr.mode; |
|
233 CPSR cpsr = val; | 238 CPSR cpsr = val; |
239 if (old_mode != cpsr.mode) { 240 tc->getITBPtr()->invalidateMiscReg(); 241 tc->getDTBPtr()->invalidateMiscReg(); 242 } 243 |
|
234 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 235 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 236 PCState pc = tc->pcState(); 237 pc.nextThumb(cpsr.t); 238 pc.nextJazelle(cpsr.j); 239 tc->pcState(pc); 240 } else if (misc_reg >= MISCREG_CP15_UNIMP_START && 241 misc_reg < MISCREG_CP15_END) { --- 62 unchanged lines hidden (view full) --- 304 break; 305 case MISCREG_SCTLR: 306 { 307 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 308 SCTLR sctlr = miscRegs[MISCREG_SCTLR]; 309 SCTLR new_sctlr = newVal; 310 new_sctlr.nmfi = (bool)sctlr.nmfi; 311 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; | 244 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 245 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 246 PCState pc = tc->pcState(); 247 pc.nextThumb(cpsr.t); 248 pc.nextJazelle(cpsr.j); 249 tc->pcState(pc); 250 } else if (misc_reg >= MISCREG_CP15_UNIMP_START && 251 misc_reg < MISCREG_CP15_END) { --- 62 unchanged lines hidden (view full) --- 314 break; 315 case MISCREG_SCTLR: 316 { 317 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 318 SCTLR sctlr = miscRegs[MISCREG_SCTLR]; 319 SCTLR new_sctlr = newVal; 320 new_sctlr.nmfi = (bool)sctlr.nmfi; 321 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; |
322 tc->getITBPtr()->invalidateMiscReg(); 323 tc->getDTBPtr()->invalidateMiscReg(); |
|
312 return; 313 } 314 case MISCREG_TLBTR: 315 case MISCREG_MVFR0: 316 case MISCREG_MVFR1: 317 case MISCREG_MPIDR: 318 case MISCREG_FPSID: 319 return; --- 101 unchanged lines hidden (view full) --- 421 miscRegs[MISCREG_PAR] = 422 (fsr.ext << 6) | 423 (fsr.fsHigh << 5) | 424 (fsr.fsLow << 1) | 425 0x1; // F bit 426 } 427 return; 428 } | 324 return; 325 } 326 case MISCREG_TLBTR: 327 case MISCREG_MVFR0: 328 case MISCREG_MVFR1: 329 case MISCREG_MPIDR: 330 case MISCREG_FPSID: 331 return; --- 101 unchanged lines hidden (view full) --- 433 miscRegs[MISCREG_PAR] = 434 (fsr.ext << 6) | 435 (fsr.fsHigh << 5) | 436 (fsr.fsLow << 1) | 437 0x1; // F bit 438 } 439 return; 440 } |
441 case MISCREG_CONTEXTIDR: 442 case MISCREG_PRRR: 443 case MISCREG_NMRR: 444 case MISCREG_DACR: 445 tc->getITBPtr()->invalidateMiscReg(); 446 tc->getDTBPtr()->invalidateMiscReg(); 447 break; 448 |
|
429 } 430 } 431 setMiscRegNoEffect(misc_reg, newVal); 432} 433 434} | 449 } 450 } 451 setMiscRegNoEffect(misc_reg, newVal); 452} 453 454} |