isa.cc (7720:65d338a8dba4) isa.cc (7731:e1eace3a118a)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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175 }
176 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
177 misc_reg < MISCREG_CP15_END) {
178 panic("Unimplemented CP15 register %s read.\n",
179 miscRegName[misc_reg]);
180 }
181 switch (misc_reg) {
182 case MISCREG_CLIDR:
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 166 unchanged lines hidden (view full) ---

175 }
176 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
177 misc_reg < MISCREG_CP15_END) {
178 panic("Unimplemented CP15 register %s read.\n",
179 miscRegName[misc_reg]);
180 }
181 switch (misc_reg) {
182 case MISCREG_CLIDR:
183 warn("The clidr register always reports 0 caches.\n");
183 warn_once("The clidr register always reports 0 caches.\n");
184 break;
185 case MISCREG_CCSIDR:
184 break;
185 case MISCREG_CCSIDR:
186 warn("The ccsidr register isn't implemented and "
186 warn_once("The ccsidr register isn't implemented and "
187 "always reads as 0.\n");
188 break;
189 case MISCREG_ID_PFR0:
190 warn("Returning thumbEE disabled for now since we don't support CP14"
191 "config registers and jumping to ThumbEE vectors\n");
192 return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM
193 case MISCREG_ID_MMFR0:
194 return 0x03; //VMSAz7

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263 newCpacr.cp11 = valCpacr.cp11;
264 //XXX d32dis isn't implemented. The manual says whether or not
265 //it works is implementation defined.
266 newCpacr.asedis = valCpacr.asedis;
267 newVal = newCpacr;
268 }
269 break;
270 case MISCREG_CSSELR:
187 "always reads as 0.\n");
188 break;
189 case MISCREG_ID_PFR0:
190 warn("Returning thumbEE disabled for now since we don't support CP14"
191 "config registers and jumping to ThumbEE vectors\n");
192 return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM
193 case MISCREG_ID_MMFR0:
194 return 0x03; //VMSAz7

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263 newCpacr.cp11 = valCpacr.cp11;
264 //XXX d32dis isn't implemented. The manual says whether or not
265 //it works is implementation defined.
266 newCpacr.asedis = valCpacr.asedis;
267 newVal = newCpacr;
268 }
269 break;
270 case MISCREG_CSSELR:
271 warn("The csselr register isn't implemented.\n");
271 warn_once("The csselr register isn't implemented.\n");
272 break;
273 case MISCREG_FPSCR:
274 {
275 const uint32_t ones = (uint32_t)(-1);
276 FPSCR fpscrMask = 0;
277 fpscrMask.ioc = ones;
278 fpscrMask.dzc = ones;
279 fpscrMask.ofc = ones;

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314 case MISCREG_TLBTR:
315 case MISCREG_MVFR0:
316 case MISCREG_MVFR1:
317 case MISCREG_MPIDR:
318 case MISCREG_FPSID:
319 return;
320 case MISCREG_TLBIALLIS:
321 case MISCREG_TLBIALL:
272 break;
273 case MISCREG_FPSCR:
274 {
275 const uint32_t ones = (uint32_t)(-1);
276 FPSCR fpscrMask = 0;
277 fpscrMask.ioc = ones;
278 fpscrMask.dzc = ones;
279 fpscrMask.ofc = ones;

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314 case MISCREG_TLBTR:
315 case MISCREG_MVFR0:
316 case MISCREG_MVFR1:
317 case MISCREG_MPIDR:
318 case MISCREG_FPSID:
319 return;
320 case MISCREG_TLBIALLIS:
321 case MISCREG_TLBIALL:
322 warn("Need to flush all TLBs in MP\n");
322 warn_once("Need to flush all TLBs in MP\n");
323 tc->getITBPtr()->flushAll();
324 tc->getDTBPtr()->flushAll();
325 return;
326 case MISCREG_ITLBIALL:
327 tc->getITBPtr()->flushAll();
328 return;
329 case MISCREG_DTLBIALL:
330 tc->getDTBPtr()->flushAll();
331 return;
332 case MISCREG_TLBIMVAIS:
333 case MISCREG_TLBIMVA:
323 tc->getITBPtr()->flushAll();
324 tc->getDTBPtr()->flushAll();
325 return;
326 case MISCREG_ITLBIALL:
327 tc->getITBPtr()->flushAll();
328 return;
329 case MISCREG_DTLBIALL:
330 tc->getDTBPtr()->flushAll();
331 return;
332 case MISCREG_TLBIMVAIS:
333 case MISCREG_TLBIMVA:
334 warn("Need to flush all TLBs in MP\n");
334 warn_once("Need to flush all TLBs in MP\n");
335 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
336 bits(newVal, 7,0));
337 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
338 bits(newVal, 7,0));
339 return;
340 case MISCREG_TLBIASIDIS:
341 case MISCREG_TLBIASID:
335 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
336 bits(newVal, 7,0));
337 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
338 bits(newVal, 7,0));
339 return;
340 case MISCREG_TLBIASIDIS:
341 case MISCREG_TLBIASID:
342 warn("Need to flush all TLBs in MP\n");
342 warn_once("Need to flush all TLBs in MP\n");
343 tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
344 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
345 return;
346 case MISCREG_TLBIMVAAIS:
347 case MISCREG_TLBIMVAA:
343 tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
344 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
345 return;
346 case MISCREG_TLBIMVAAIS:
347 case MISCREG_TLBIMVAA:
348 warn("Need to flush all TLBs in MP\n");
348 warn_once("Need to flush all TLBs in MP\n");
349 tc->getITBPtr()->flushMva(mbits(newVal, 31,12));
350 tc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
351 return;
352 case MISCREG_ITLBIMVA:
353 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
354 bits(newVal, 7,0));
355 return;
356 case MISCREG_DTLBIMVA:

--- 78 unchanged lines hidden --- 		349 tc->getITBPtr()->flushMva(mbits(newVal, 31,12));
350 tc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
351 return;
352 case MISCREG_ITLBIMVA:
353 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
354 bits(newVal, 7,0));
355 return;
356 case MISCREG_DTLBIMVA:

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