isa.cc (7692:8173327c9c65) isa.cc (7720:65d338a8dba4)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 154 unchanged lines hidden (view full) ---

163}
164
165
166MiscReg
167ISA::readMiscReg(int misc_reg, ThreadContext *tc)
168{
169 if (misc_reg == MISCREG_CPSR) {
170 CPSR cpsr = miscRegs[misc_reg];
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 154 unchanged lines hidden (view full) ---

163}
164
165
166MiscReg
167ISA::readMiscReg(int misc_reg, ThreadContext *tc)
168{
169 if (misc_reg == MISCREG_CPSR) {
170 CPSR cpsr = miscRegs[misc_reg];
171 Addr pc = tc->readPC();
172 if (pc & (ULL(1) << PcJBitShift))
173 cpsr.j = 1;
174 else
175 cpsr.j = 0;
176 if (isThumb(pc))
177 cpsr.t = 1;
178 else
179 cpsr.t = 0;
171 PCState pc = tc->pcState();
172 cpsr.j = pc.jazelle() ? 1 : 0;
173 cpsr.t = pc.thumb() ? 1 : 0;
180 return cpsr;
181 }
182 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
183 misc_reg < MISCREG_CP15_END) {
184 panic("Unimplemented CP15 register %s read.\n",
185 miscRegName[misc_reg]);
186 }
187 switch (misc_reg) {

--- 46 unchanged lines hidden (view full) ---

234ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
235{
236 MiscReg newVal = val;
237 if (misc_reg == MISCREG_CPSR) {
238 updateRegMap(val);
239 CPSR cpsr = val;
240 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
241 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
174 return cpsr;
175 }
176 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
177 misc_reg < MISCREG_CP15_END) {
178 panic("Unimplemented CP15 register %s read.\n",
179 miscRegName[misc_reg]);
180 }
181 switch (misc_reg) {

--- 46 unchanged lines hidden (view full) ---

228ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
229{
230 MiscReg newVal = val;
231 if (misc_reg == MISCREG_CPSR) {
232 updateRegMap(val);
233 CPSR cpsr = val;
234 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
235 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
242 Addr npc = tc->readNextPC() & ~PcModeMask;
243 if (cpsr.j)
244 npc = npc | PcJBit;
245 if (cpsr.t)
246 npc = npc | PcTBit;
247
248 tc->setNextPC(npc);
236 PCState pc = tc->pcState();
237 pc.nextThumb(cpsr.t);
238 pc.nextJazelle(cpsr.j);
239 tc->pcState(pc);
249 } else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
250 misc_reg < MISCREG_CP15_END) {
251 panic("Unimplemented CP15 register %s wrote with %#x.\n",
252 miscRegName[misc_reg], val);
253 } else {
254 switch (misc_reg) {
255 case MISCREG_ITSTATE:
256 {

--- 152 unchanged lines hidden (view full) ---

409 break;
410 case MISCREG_V2PCWUW:
411 flags = TLB::MustBeOne | TLB::UserMode;
412 mode = BaseTLB::Write;
413 break;
414 default:
415 panic("Security Extensions not implemented!");
416 }
240 } else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
241 misc_reg < MISCREG_CP15_END) {
242 panic("Unimplemented CP15 register %s wrote with %#x.\n",
243 miscRegName[misc_reg], val);
244 } else {
245 switch (misc_reg) {
246 case MISCREG_ITSTATE:
247 {

--- 152 unchanged lines hidden (view full) ---

400 break;
401 case MISCREG_V2PCWUW:
402 flags = TLB::MustBeOne | TLB::UserMode;
403 mode = BaseTLB::Write;
404 break;
405 default:
406 panic("Security Extensions not implemented!");
407 }
417 req->setVirt(0, val, 1, flags, tc->readPC());
408 req->setVirt(0, val, 1, flags, tc->pcState().pc());
418 fault = tc->getDTBPtr()->translateAtomic(req, tc, mode);
419 if (fault == NoFault) {
420 miscRegs[MISCREG_PAR] =
421 (req->getPaddr() & 0xfffff000) |
422 (tc->getDTBPtr()->getAttr() );
423 DPRINTF(MiscRegs,
424 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
425 val, miscRegs[MISCREG_PAR]);

--- 18 unchanged lines hidden --- 		409 fault = tc->getDTBPtr()->translateAtomic(req, tc, mode);
410 if (fault == NoFault) {
411 miscRegs[MISCREG_PAR] =
412 (req->getPaddr() & 0xfffff000) |
413 (tc->getDTBPtr()->getAttr() );
414 DPRINTF(MiscRegs,
415 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
416 val, miscRegs[MISCREG_PAR]);

--- 18 unchanged lines hidden ---