isa.cc (7678:f19b6a3a8cec) isa.cc (7692:8173327c9c65)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 159 unchanged lines hidden (view full) ---

168{
169 if (misc_reg == MISCREG_CPSR) {
170 CPSR cpsr = miscRegs[misc_reg];
171 Addr pc = tc->readPC();
172 if (pc & (ULL(1) << PcJBitShift))
173 cpsr.j = 1;
174 else
175 cpsr.j = 0;
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 159 unchanged lines hidden (view full) ---

168{
169 if (misc_reg == MISCREG_CPSR) {
170 CPSR cpsr = miscRegs[misc_reg];
171 Addr pc = tc->readPC();
172 if (pc & (ULL(1) << PcJBitShift))
173 cpsr.j = 1;
174 else
175 cpsr.j = 0;
176 if (pc & (ULL(1) << PcTBitShift))
176 if (isThumb(pc))
177 cpsr.t = 1;
178 else
179 cpsr.t = 0;
180 return cpsr;
181 }
182 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
183 misc_reg < MISCREG_CP15_END) {
184 panic("Unimplemented CP15 register %s read.\n",

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236 MiscReg newVal = val;
237 if (misc_reg == MISCREG_CPSR) {
238 updateRegMap(val);
239 CPSR cpsr = val;
240 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
241 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
242 Addr npc = tc->readNextPC() & ~PcModeMask;
243 if (cpsr.j)
177 cpsr.t = 1;
178 else
179 cpsr.t = 0;
180 return cpsr;
181 }
182 if (misc_reg >= MISCREG_CP15_UNIMP_START &&
183 misc_reg < MISCREG_CP15_END) {
184 panic("Unimplemented CP15 register %s read.\n",

--- 51 unchanged lines hidden (view full) ---

236 MiscReg newVal = val;
237 if (misc_reg == MISCREG_CPSR) {
238 updateRegMap(val);
239 CPSR cpsr = val;
240 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
241 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
242 Addr npc = tc->readNextPC() & ~PcModeMask;
243 if (cpsr.j)
244 npc = npc | (ULL(1) << PcJBitShift);
244 npc = npc | PcJBit;
245 if (cpsr.t)
245 if (cpsr.t)
246 npc = npc | (ULL(1) << PcTBitShift);
246 npc = npc | PcTBit;
247
248 tc->setNextPC(npc);
249 } else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
250 misc_reg < MISCREG_CP15_END) {
251 panic("Unimplemented CP15 register %s wrote with %#x.\n",
252 miscRegName[misc_reg], val);
253 } else {
254 switch (misc_reg) {

--- 189 unchanged lines hidden --- 		247
248 tc->setNextPC(npc);
249 } else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
250 misc_reg < MISCREG_CP15_END) {
251 panic("Unimplemented CP15 register %s wrote with %#x.\n",
252 miscRegName[misc_reg], val);
253 } else {
254 switch (misc_reg) {

--- 189 unchanged lines hidden ---