isa.cc (7644:62873d5c2bfc) isa.cc (7645:873b90fa0eca)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 60 unchanged lines hidden (view full) ---

69 /* Start with an event in the mailbox */
70 miscRegs[MISCREG_SEV_MAILBOX] = 1;
71
72 /*
73 * Implemented = '5' from "M5",
74 * Variant = 0,
75 */
76 miscRegs[MISCREG_MIDR] =
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 60 unchanged lines hidden (view full) ---

69 /* Start with an event in the mailbox */
70 miscRegs[MISCREG_SEV_MAILBOX] = 1;
71
72 /*
73 * Implemented = '5' from "M5",
74 * Variant = 0,
75 */
76 miscRegs[MISCREG_MIDR] =
77 (0x35 << 24) | //Implementor is '5' from "M5"
78 (0 << 20) | //Variant
79 (0xf << 16) | //Architecture from CPUID scheme
80 (0 << 4) | //Primary part number
81 (0 << 0) | //Revision
77 (0x35 << 24) | // Implementor is '5' from "M5"
78 (0 << 20) | // Variant
79 (0xf << 16) | // Architecture from CPUID scheme
80 (0xf00 << 4) | // Primary part number
81 (0 << 0) | // Revision
82 0;
83
84 // Separate Instruction and Data TLBs.
85 miscRegs[MISCREG_TLBTR] = 1;
86
87 MVFR0 mvfr0 = 0;
88 mvfr0.advSimdRegisters = 2;
89 mvfr0.singlePrecision = 2;

--- 353 unchanged lines hidden --- 		82 0;
83
84 // Separate Instruction and Data TLBs.
85 miscRegs[MISCREG_TLBTR] = 1;
86
87 MVFR0 mvfr0 = 0;
88 mvfr0.advSimdRegisters = 2;
89 mvfr0.singlePrecision = 2;

--- 353 unchanged lines hidden ---