isa.cc (7614:763e836c0e70) isa.cc (7640:5286a8a469c5)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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61 sctlr.u = 1;
62 sctlr.xp = 1;
63 sctlr.rao2 = 1;
64 sctlr.rao3 = 1;
65 sctlr.rao4 = 1;
66 miscRegs[MISCREG_SCTLR] = sctlr;
67 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
68
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 52 unchanged lines hidden (view full) ---

61 sctlr.u = 1;
62 sctlr.xp = 1;
63 sctlr.rao2 = 1;
64 sctlr.rao3 = 1;
65 sctlr.rao4 = 1;
66 miscRegs[MISCREG_SCTLR] = sctlr;
67 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
68
69
70 /*
71 * Technically this should be 0, but we don't support those
72 * settings.
73 */
74 CPACR cpacr = 0;
75 // Enable CP 10, 11
76 cpacr.cp10 = 0x3;
77 cpacr.cp11 = 0x3;
78 miscRegs[MISCREG_CPACR] = cpacr;
79
80 /* Start with an event in the mailbox */
81 miscRegs[MISCREG_SEV_MAILBOX] = 1;
82
83 /*
84 * Implemented = '5' from "M5",
85 * Variant = 0,
86 */
87 miscRegs[MISCREG_MIDR] =

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273 }
274 break;
275 case MISCREG_CPACR:
276 {
277 CPACR newCpacr = 0;
278 CPACR valCpacr = val;
279 newCpacr.cp10 = valCpacr.cp10;
280 newCpacr.cp11 = valCpacr.cp11;
69 /* Start with an event in the mailbox */
70 miscRegs[MISCREG_SEV_MAILBOX] = 1;
71
72 /*
73 * Implemented = '5' from "M5",
74 * Variant = 0,
75 */
76 miscRegs[MISCREG_MIDR] =

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262 }
263 break;
264 case MISCREG_CPACR:
265 {
266 CPACR newCpacr = 0;
267 CPACR valCpacr = val;
268 newCpacr.cp10 = valCpacr.cp10;
269 newCpacr.cp11 = valCpacr.cp11;
281 if (newCpacr.cp10 != 0x3 || newCpacr.cp11 != 3) {
282 panic("Disabling coprocessors isn't implemented.\n");
283 }
270 //XXX d32dis isn't implemented. The manual says whether or not
271 //it works is implementation defined.
272 newCpacr.asedis = valCpacr.asedis;
284 newVal = newCpacr;
285 }
286 break;
287 case MISCREG_CSSELR:
288 warn("The csselr register isn't implemented.\n");
289 break;
290 case MISCREG_FPSCR:
291 {

--- 160 unchanged lines hidden --- 		273 newVal = newCpacr;
274 }
275 break;
276 case MISCREG_CSSELR:
277 warn("The csselr register isn't implemented.\n");
278 break;
279 case MISCREG_FPSCR:
280 {

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