isa.cc (7442:2dc67291f730) isa.cc (7583:665d71561298)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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207 warn("The clidr register always reports 0 caches.\n");
208 break;
209 case MISCREG_CCSIDR:
210 warn("The ccsidr register isn't implemented and "
211 "always reads as 0.\n");
212 break;
213 case MISCREG_ID_PFR0:
214 return 0x1031; // ThumbEE | !Jazelle | Thumb | ARM
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 198 unchanged lines hidden (view full) ---

207 warn("The clidr register always reports 0 caches.\n");
208 break;
209 case MISCREG_CCSIDR:
210 warn("The ccsidr register isn't implemented and "
211 "always reads as 0.\n");
212 break;
213 case MISCREG_ID_PFR0:
214 return 0x1031; // ThumbEE | !Jazelle | Thumb | ARM
215 case MISCREG_ID_MMFR0:
216 return 0x03; //VMSAz7
217 case MISCREG_CTR:
218 return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact
219 case MISCREG_ACTLR:
220 warn("Not doing anything for miscreg ACTLR\n");
221 break;
222 case MISCREG_PMCR:
223 case MISCREG_PMCCNTR:
224 case MISCREG_PMSELR:
225 warn("Not doing anyhting for read to miscreg %s\n",
226 miscRegName[misc_reg]);
227 break;
228
215 }
216 return readMiscRegNoEffect(misc_reg);
217}
218
219void
220ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
221{
222 assert(misc_reg < NumMiscRegs);

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389 bits(newVal, 7,0));
390 return;
391 case MISCREG_ITLBIASID:
392 tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
393 return;
394 case MISCREG_DTLBIASID:
395 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
396 return;
229 }
230 return readMiscRegNoEffect(misc_reg);
231}
232
233void
234ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
235{
236 assert(misc_reg < NumMiscRegs);

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403 bits(newVal, 7,0));
404 return;
405 case MISCREG_ITLBIASID:
406 tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
407 return;
408 case MISCREG_DTLBIASID:
409 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
410 return;
411 case MISCREG_ACTLR:
412 warn("Not doing anything for write of miscreg ACTLR\n");
413 break;
414 case MISCREG_PMCR:
415 case MISCREG_PMCCNTR:
416 case MISCREG_PMSELR:
417 warn("Not doing anything for write to miscreg %s\n",
418 miscRegName[misc_reg]);
419 break;
397 case MISCREG_V2PCWPR:
398 case MISCREG_V2PCWPW:
399 case MISCREG_V2PCWUR:
400 case MISCREG_V2PCWUW:
401 case MISCREG_V2POWPR:
402 case MISCREG_V2POWPW:
403 case MISCREG_V2POWUR:
404 case MISCREG_V2POWUW:

--- 52 unchanged lines hidden --- 		420 case MISCREG_V2PCWPR:
421 case MISCREG_V2PCWPW:
422 case MISCREG_V2PCWUR:
423 case MISCREG_V2PCWUW:
424 case MISCREG_V2POWPR:
425 case MISCREG_V2POWPW:
426 case MISCREG_V2POWUR:
427 case MISCREG_V2POWUW:

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