isa.cc (7436:b578349f9371) isa.cc (7442:2dc67291f730)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 410 unchanged lines hidden (view full) ---

419 case MISCREG_V2PCWUR:
420 flags = TLB::MustBeOne | TLB::UserMode;
421 mode = BaseTLB::Read;
422 break;
423 case MISCREG_V2PCWUW:
424 flags = TLB::MustBeOne | TLB::UserMode;
425 mode = BaseTLB::Write;
426 break;
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 410 unchanged lines hidden (view full) ---

419 case MISCREG_V2PCWUR:
420 flags = TLB::MustBeOne | TLB::UserMode;
421 mode = BaseTLB::Read;
422 break;
423 case MISCREG_V2PCWUW:
424 flags = TLB::MustBeOne | TLB::UserMode;
425 mode = BaseTLB::Write;
426 break;
427 case MISCREG_V2POWPR:
428 case MISCREG_V2POWPW:
429 case MISCREG_V2POWUR:
430 case MISCREG_V2POWUW:
427 default:
431 panic("Security Extensions not implemented!");
432 }
433 req->setVirt(0, val, 1, flags, tc->readPC());
434 fault = tc->getDTBPtr()->translateAtomic(req, tc, mode);
435 if (fault == NoFault) {
436 miscRegs[MISCREG_PAR] =
437 (req->getPaddr() & 0xfffff000) |
438 (tc->getDTBPtr()->getAttr() );

--- 21 unchanged lines hidden --- 		428 panic("Security Extensions not implemented!");
429 }
430 req->setVirt(0, val, 1, flags, tc->readPC());
431 fault = tc->getDTBPtr()->translateAtomic(req, tc, mode);
432 if (fault == NoFault) {
433 miscRegs[MISCREG_PAR] =
434 (req->getPaddr() & 0xfffff000) |
435 (tc->getDTBPtr()->getAttr() );

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