isa.cc (7405:7a938baf14be) isa.cc (7406:ddc26bd4ea7d)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 201 unchanged lines hidden (view full) ---

210 {
211 const uint32_t fpexcMask = 0x60000000;
212 newVal = (newVal & fpexcMask) |
213 (miscRegs[MISCREG_FPEXC] & ~fpexcMask);
214 }
215 break;
216 case MISCREG_SCTLR:
217 {
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 201 unchanged lines hidden (view full) ---

210 {
211 const uint32_t fpexcMask = 0x60000000;
212 newVal = (newVal & fpexcMask) |
213 (miscRegs[MISCREG_FPEXC] & ~fpexcMask);
214 }
215 break;
216 case MISCREG_SCTLR:
217 {
218 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
218 SCTLR sctlr = miscRegs[MISCREG_SCTLR];
219 SCTLR new_sctlr = newVal;
220 new_sctlr.nmfi = (bool)sctlr.nmfi;
221 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr;
222 return;
223 }
224 case MISCREG_TLBTR:
225 case MISCREG_MVFR0:

--- 55 unchanged lines hidden --- 		219 SCTLR sctlr = miscRegs[MISCREG_SCTLR];
220 SCTLR new_sctlr = newVal;
221 new_sctlr.nmfi = (bool)sctlr.nmfi;
222 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr;
223 return;
224 }
225 case MISCREG_TLBTR:
226 case MISCREG_MVFR0:

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