isa.cc (14000:d85c61dc0b5c) | isa.cc (14128:6ed23d07d0d1) |
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1/* | 1/* |
2 * Copyright (c) 2010-2018 ARM Limited | 2 * Copyright (c) 2010-2019 ARM Limited |
3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 75 unchanged lines hidden (view full) --- 86 highestELIs64 = system->highestELIs64(); 87 haveSecurity = system->haveSecurity(); 88 haveLPAE = system->haveLPAE(); 89 haveCrypto = system->haveCrypto(); 90 haveVirtualization = system->haveVirtualization(); 91 haveLargeAsid64 = system->haveLargeAsid64(); 92 physAddrRange = system->physAddrRange(); 93 haveSVE = system->haveSVE(); | 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 75 unchanged lines hidden (view full) --- 86 highestELIs64 = system->highestELIs64(); 87 haveSecurity = system->haveSecurity(); 88 haveLPAE = system->haveLPAE(); 89 haveCrypto = system->haveCrypto(); 90 haveVirtualization = system->haveVirtualization(); 91 haveLargeAsid64 = system->haveLargeAsid64(); 92 physAddrRange = system->physAddrRange(); 93 haveSVE = system->haveSVE(); |
94 havePAN = system->havePAN(); |
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94 sveVL = system->sveVL(); 95 } else { 96 highestELIs64 = true; // ArmSystem::highestELIs64 does the same 97 haveSecurity = haveLPAE = haveVirtualization = false; 98 haveCrypto = true; 99 haveLargeAsid64 = false; 100 physAddrRange = 32; // dummy value 101 haveSVE = true; | 95 sveVL = system->sveVL(); 96 } else { 97 highestELIs64 = true; // ArmSystem::highestELIs64 does the same 98 haveSecurity = haveLPAE = haveVirtualization = false; 99 haveCrypto = true; 100 haveLargeAsid64 = false; 101 physAddrRange = 32; // dummy value 102 haveSVE = true; |
103 havePAN = false; |
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102 sveVL = p->sve_vl_se; 103 } 104 105 // Initial rename mode depends on highestEL 106 const_cast<Enums::VecRegRenameMode&>(_vecRegRenameMode) = 107 highestELIs64 ? Enums::Full : Enums::Elem; 108 109 initializeMiscRegMetadata(); --- 276 unchanged lines hidden (view full) --- 386 // Physical address size 387 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 388 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 389 encodePhysAddrRange64(physAddrRange)); 390 // Crypto 391 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits( 392 miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4, 393 haveCrypto ? 0x1112 : 0x0); | 104 sveVL = p->sve_vl_se; 105 } 106 107 // Initial rename mode depends on highestEL 108 const_cast<Enums::VecRegRenameMode&>(_vecRegRenameMode) = 109 highestELIs64 ? Enums::Full : Enums::Elem; 110 111 initializeMiscRegMetadata(); --- 276 unchanged lines hidden (view full) --- 388 // Physical address size 389 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 390 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 391 encodePhysAddrRange64(physAddrRange)); 392 // Crypto 393 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits( 394 miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4, 395 haveCrypto ? 0x1112 : 0x0); |
396 // PAN 397 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits( 398 miscRegs[MISCREG_ID_AA64MMFR1_EL1], 23, 20, 399 havePAN ? 0x1 : 0x0); |
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394} 395 396void 397ISA::startup(ThreadContext *tc) 398{ 399 pmu->setThreadContext(tc); 400 401 if (system) { --- 233 unchanged lines hidden (view full) --- 635 case MISCREG_SPSEL: 636 { 637 return miscRegs[MISCREG_CPSR] & 0x1; 638 } 639 case MISCREG_CURRENTEL: 640 { 641 return miscRegs[MISCREG_CPSR] & 0xc; 642 } | 400} 401 402void 403ISA::startup(ThreadContext *tc) 404{ 405 pmu->setThreadContext(tc); 406 407 if (system) { --- 233 unchanged lines hidden (view full) --- 641 case MISCREG_SPSEL: 642 { 643 return miscRegs[MISCREG_CPSR] & 0x1; 644 } 645 case MISCREG_CURRENTEL: 646 { 647 return miscRegs[MISCREG_CPSR] & 0xc; 648 } |
649 case MISCREG_PAN: 650 { 651 return miscRegs[MISCREG_CPSR] & 0x400000; 652 } |
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643 case MISCREG_L2CTLR: 644 { 645 // mostly unimplemented, just set NumCPUs field from sim and return 646 L2CTLR l2ctlr = 0; 647 // b00:1CPU to b11:4CPUs 648 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 649 return l2ctlr; 650 } --- 1224 unchanged lines hidden (view full) --- 1875 case MISCREG_CURRENTEL: 1876 { 1877 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1878 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1879 newVal = cpsr; 1880 misc_reg = MISCREG_CPSR; 1881 } 1882 break; | 653 case MISCREG_L2CTLR: 654 { 655 // mostly unimplemented, just set NumCPUs field from sim and return 656 L2CTLR l2ctlr = 0; 657 // b00:1CPU to b11:4CPUs 658 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 659 return l2ctlr; 660 } --- 1224 unchanged lines hidden (view full) --- 1885 case MISCREG_CURRENTEL: 1886 { 1887 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1888 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1889 newVal = cpsr; 1890 misc_reg = MISCREG_CPSR; 1891 } 1892 break; |
1893 case MISCREG_PAN: 1894 { 1895 // PAN is affecting data accesses 1896 getDTBPtr(tc)->invalidateMiscReg(); 1897 1898 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1899 cpsr.pan = (uint8_t) ((CPSR) newVal).pan; 1900 newVal = cpsr; 1901 misc_reg = MISCREG_CPSR; 1902 } 1903 break; |
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1883 case MISCREG_AT_S1E1R_Xt: 1884 case MISCREG_AT_S1E1W_Xt: 1885 case MISCREG_AT_S1E0R_Xt: 1886 case MISCREG_AT_S1E0W_Xt: 1887 case MISCREG_AT_S1E2R_Xt: 1888 case MISCREG_AT_S1E2W_Xt: 1889 case MISCREG_AT_S12E1R_Xt: 1890 case MISCREG_AT_S12E1W_Xt: --- 124 unchanged lines hidden (view full) --- 2015 val, fsr, newVal); 2016 } 2017 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 2018 return; 2019 } 2020 case MISCREG_SPSR_EL3: 2021 case MISCREG_SPSR_EL2: 2022 case MISCREG_SPSR_EL1: | 1904 case MISCREG_AT_S1E1R_Xt: 1905 case MISCREG_AT_S1E1W_Xt: 1906 case MISCREG_AT_S1E0R_Xt: 1907 case MISCREG_AT_S1E0W_Xt: 1908 case MISCREG_AT_S1E2R_Xt: 1909 case MISCREG_AT_S1E2W_Xt: 1910 case MISCREG_AT_S12E1R_Xt: 1911 case MISCREG_AT_S12E1W_Xt: --- 124 unchanged lines hidden (view full) --- 2036 val, fsr, newVal); 2037 } 2038 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 2039 return; 2040 } 2041 case MISCREG_SPSR_EL3: 2042 case MISCREG_SPSR_EL2: 2043 case MISCREG_SPSR_EL1: |
2023 // Force bits 23:21 to 0 2024 newVal = val & ~(0x7 << 21); 2025 break; | 2044 { 2045 RegVal spsr_mask = havePAN ? 2046 ~(0x5 << 21) : ~(0x7 << 21); 2047 2048 newVal = val & spsr_mask; 2049 break; 2050 } |
2026 case MISCREG_L2CTLR: 2027 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 2028 miscRegName[misc_reg], uint32_t(val)); 2029 break; 2030 2031 // Generic Timer registers 2032 case MISCREG_CNTHV_CTL_EL2: 2033 case MISCREG_CNTHV_CVAL_EL2: --- 110 unchanged lines hidden --- | 2051 case MISCREG_L2CTLR: 2052 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 2053 miscRegName[misc_reg], uint32_t(val)); 2054 break; 2055 2056 // Generic Timer registers 2057 case MISCREG_CNTHV_CTL_EL2: 2058 case MISCREG_CNTHV_CVAL_EL2: --- 110 unchanged lines hidden --- |