isa.cc (13826:34a9929c35eb) isa.cc (13881:955558193370)
1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1214 // in the tlb the last level of lookup only.
1215 // TLB Invalidate by VA, Hyp mode
1216 case MISCREG_TLBIMVAH:
1217 case MISCREG_TLBIMVALH:
1218 {
1219 assert32(tc);
1220 scr = readMiscReg(MISCREG_SCR, tc);
1221
1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 1205 unchanged lines hidden (view full) ---

1214 // in the tlb the last level of lookup only.
1215 // TLB Invalidate by VA, Hyp mode
1216 case MISCREG_TLBIMVAH:
1217 case MISCREG_TLBIMVALH:
1218 {
1219 assert32(tc);
1220 scr = readMiscReg(MISCREG_SCR, tc);
1221
1222 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1222 TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns,
1223 mbits(newVal, 31,12), true);
1224
1225 tlbiOp(tc);
1226 return;
1227 }
1228 // TLB Invalidate by VA, Hyp mode, Inner Shareable
1229 case MISCREG_TLBIMVAHIS:
1230 case MISCREG_TLBIMVALHIS:
1231 {
1232 assert32(tc);
1233 scr = readMiscReg(MISCREG_SCR, tc);
1234
1223 mbits(newVal, 31,12), true);
1224
1225 tlbiOp(tc);
1226 return;
1227 }
1228 // TLB Invalidate by VA, Hyp mode, Inner Shareable
1229 case MISCREG_TLBIMVAHIS:
1230 case MISCREG_TLBIMVALHIS:
1231 {
1232 assert32(tc);
1233 scr = readMiscReg(MISCREG_SCR, tc);
1234
1235 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1235 TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns,
1236 mbits(newVal, 31,12), true);
1237
1238 tlbiOp.broadcast(tc);
1239 return;
1240 }
1241 // mcr tlbiipas2l(is) is invalidating all matching entries
1242 // regardless of the level of lookup, since in gem5 we cache
1243 // in the tlb the last level of lookup only.

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1342 tlbiOp.broadcast(tc);
1343 return;
1344 }
1345 // TLB Invalidate All, Hyp mode
1346 case MISCREG_TLBIALLH:
1347 {
1348 assert32(tc);
1349
1236 mbits(newVal, 31,12), true);
1237
1238 tlbiOp.broadcast(tc);
1239 return;
1240 }
1241 // mcr tlbiipas2l(is) is invalidating all matching entries
1242 // regardless of the level of lookup, since in gem5 we cache
1243 // in the tlb the last level of lookup only.

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1342 tlbiOp.broadcast(tc);
1343 return;
1344 }
1345 // TLB Invalidate All, Hyp mode
1346 case MISCREG_TLBIALLH:
1347 {
1348 assert32(tc);
1349
1350 TLBIALLN tlbiOp(EL1, true);
1350 TLBIALLN tlbiOp(EL2, true);
1351 tlbiOp(tc);
1352 return;
1353 }
1354 // TLB Invalidate All, Hyp mode, Inner Shareable
1355 case MISCREG_TLBIALLHIS:
1356 {
1357 assert32(tc);
1358
1351 tlbiOp(tc);
1352 return;
1353 }
1354 // TLB Invalidate All, Hyp mode, Inner Shareable
1355 case MISCREG_TLBIALLHIS:
1356 {
1357 assert32(tc);
1358
1359 TLBIALLN tlbiOp(EL1, true);
1359 TLBIALLN tlbiOp(EL2, true);
1360 tlbiOp.broadcast(tc);
1361 return;
1362 }
1363 // AArch64 TLB Invalidate All, EL3
1364 case MISCREG_TLBI_ALLE3:
1365 {
1366 assert64(tc);
1367

--- 773 unchanged lines hidden --- 		1360 tlbiOp.broadcast(tc);
1361 return;
1362 }
1363 // AArch64 TLB Invalidate All, EL3
1364 case MISCREG_TLBI_ALLE3:
1365 {
1366 assert64(tc);
1367

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