isa.cc (13599:05e9234fef20) isa.cc (13691:9c9a28fdb97f)
1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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59{
60
61ISA::ISA(Params *p)
62 : SimObject(p),
63 system(NULL),
64 _decoderFlavour(p->decoderFlavour),
65 _vecRegRenameMode(Enums::Full),
66 pmu(p->pmu),
1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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59{
60
61ISA::ISA(Params *p)
62 : SimObject(p),
63 system(NULL),
64 _decoderFlavour(p->decoderFlavour),
65 _vecRegRenameMode(Enums::Full),
66 pmu(p->pmu),
67 haveGICv3CPUInterface(false),
67 impdefAsNop(p->impdef_nop)
68{
69 miscRegs[MISCREG_SCTLR_RST] = 0;
70
71 // Hook up a dummy device if we haven't been configured with a
72 // real PMU. By using a dummy device, we don't need to check that
73 // the PMU exist every time we try to access a PMU register.
74 if (!pmu)

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91 } else {
92 highestELIs64 = true; // ArmSystem::highestELIs64 does the same
93 haveSecurity = haveLPAE = haveVirtualization = false;
94 haveCrypto = true;
95 haveLargeAsid64 = false;
96 physAddrRange = 32; // dummy value
97 }
98
68 impdefAsNop(p->impdef_nop)
69{
70 miscRegs[MISCREG_SCTLR_RST] = 0;
71
72 // Hook up a dummy device if we haven't been configured with a
73 // real PMU. By using a dummy device, we don't need to check that
74 // the PMU exist every time we try to access a PMU register.
75 if (!pmu)

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92 } else {
93 highestELIs64 = true; // ArmSystem::highestELIs64 does the same
94 haveSecurity = haveLPAE = haveVirtualization = false;
95 haveCrypto = true;
96 haveLargeAsid64 = false;
97 physAddrRange = 32; // dummy value
98 }
99
99 // GICv3 CPU interface system registers are supported
100 haveGICv3CPUInterface = false;
101
102 if (system && dynamic_cast<Gicv3 *>(system->getGIC())) {
103 haveGICv3CPUInterface = true;
104 }
105
106 // Initial rename mode depends on highestEL
107 const_cast<Enums::VecRegRenameMode&>(_vecRegRenameMode) =
108 highestELIs64 ? Enums::Full : Enums::Elem;
109
110 initializeMiscRegMetadata();
111 preUnflattenMiscReg();
112
113 clear();

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383void
384ISA::startup(ThreadContext *tc)
385{
386 pmu->setThreadContext(tc);
387
388 if (system) {
389 Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC());
390 if (gicv3) {
100 // Initial rename mode depends on highestEL
101 const_cast<Enums::VecRegRenameMode&>(_vecRegRenameMode) =
102 highestELIs64 ? Enums::Full : Enums::Elem;
103
104 initializeMiscRegMetadata();
105 preUnflattenMiscReg();
106
107 clear();

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377void
378ISA::startup(ThreadContext *tc)
379{
380 pmu->setThreadContext(tc);
381
382 if (system) {
383 Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC());
384 if (gicv3) {
385 haveGICv3CPUInterface = true;
391 gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
392 gicv3CpuInterface->setISA(this);
393 }
394 }
395}
396
397
398RegVal

--- 1640 unchanged lines hidden --- 		386 gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
387 gicv3CpuInterface->setISA(this);
388 }
389 }
390}
391
392
393RegVal

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