isa.cc (13582:989577bf6abc) isa.cc (13599:05e9234fef20)
1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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57
58namespace ArmISA
59{
60
61ISA::ISA(Params *p)
62 : SimObject(p),
63 system(NULL),
64 _decoderFlavour(p->decoderFlavour),
1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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57
58namespace ArmISA
59{
60
61ISA::ISA(Params *p)
62 : SimObject(p),
63 system(NULL),
64 _decoderFlavour(p->decoderFlavour),
65 _vecRegRenameMode(p->vecRegRenameMode),
65 _vecRegRenameMode(Enums::Full),
66 pmu(p->pmu),
67 impdefAsNop(p->impdef_nop)
68{
69 miscRegs[MISCREG_SCTLR_RST] = 0;
70
71 // Hook up a dummy device if we haven't been configured with a
72 // real PMU. By using a dummy device, we don't need to check that
73 // the PMU exist every time we try to access a PMU register.

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98
99 // GICv3 CPU interface system registers are supported
100 haveGICv3CPUInterface = false;
101
102 if (system && dynamic_cast<Gicv3 *>(system->getGIC())) {
103 haveGICv3CPUInterface = true;
104 }
105
66 pmu(p->pmu),
67 impdefAsNop(p->impdef_nop)
68{
69 miscRegs[MISCREG_SCTLR_RST] = 0;
70
71 // Hook up a dummy device if we haven't been configured with a
72 // real PMU. By using a dummy device, we don't need to check that
73 // the PMU exist every time we try to access a PMU register.

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98
99 // GICv3 CPU interface system registers are supported
100 haveGICv3CPUInterface = false;
101
102 if (system && dynamic_cast<Gicv3 *>(system->getGIC())) {
103 haveGICv3CPUInterface = true;
104 }
105
106 // Initial rename mode depends on highestEL
107 const_cast<Enums::VecRegRenameMode&>(_vecRegRenameMode) =
108 highestELIs64 ? Enums::Full : Enums::Elem;
109
106 initializeMiscRegMetadata();
107 preUnflattenMiscReg();
108
109 clear();
110}
111
112std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS);
113

--- 1921 unchanged lines hidden --- 		110 initializeMiscRegMetadata();
111 preUnflattenMiscReg();
112
113 clear();
114}
115
116std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS);
117

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