isa.cc (13581:b6dcd0183747) | isa.cc (13582:989577bf6abc) |
---|---|
1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 696 unchanged lines hidden (view full) --- 705 default: 706 break; 707 708 } 709 return readMiscRegNoEffect(misc_reg); 710} 711 712void | 1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 696 unchanged lines hidden (view full) --- 705 default: 706 break; 707 708 } 709 return readMiscRegNoEffect(misc_reg); 710} 711 712void |
713ISA::setMiscRegNoEffect(int misc_reg, const RegVal &val) | 713ISA::setMiscRegNoEffect(int misc_reg, RegVal val) |
714{ 715 assert(misc_reg < NumMiscRegs); 716 717 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 718 const auto &map = getMiscIndices(misc_reg); 719 int lower = map.first, upper = map.second; 720 721 auto v = (val & ~reg.wi()) | reg.rao(); --- 5 unchanged lines hidden (view full) --- 727 } else { 728 miscRegs[lower] = v; 729 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 730 misc_reg, lower, v); 731 } 732} 733 734void | 714{ 715 assert(misc_reg < NumMiscRegs); 716 717 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 718 const auto &map = getMiscIndices(misc_reg); 719 int lower = map.first, upper = map.second; 720 721 auto v = (val & ~reg.wi()) | reg.rao(); --- 5 unchanged lines hidden (view full) --- 727 } else { 728 miscRegs[lower] = v; 729 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 730 misc_reg, lower, v); 731 } 732} 733 734void |
735ISA::setMiscReg(int misc_reg, const RegVal &val, ThreadContext *tc) | 735ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) |
736{ 737 738 RegVal newVal = val; 739 bool secure_lookup; 740 SCR scr; 741 742 if (misc_reg == MISCREG_CPSR) { 743 updateRegMap(val); --- 1291 unchanged lines hidden --- | 736{ 737 738 RegVal newVal = val; 739 bool secure_lookup; 740 SCR scr; 741 742 if (misc_reg == MISCREG_CPSR) { 743 updateRegMap(val); --- 1291 unchanged lines hidden --- |