Cross Reference: /gem5/src/arch/arm/isa.cc

1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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386 if (gicv3) {
387 gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
388 gicv3CpuInterface->setISA(this);
389 }
390 }
391}
392
393

394MiscReg

394RegVal

395ISA::readMiscRegNoEffect(int misc_reg) const
396{
397 assert(misc_reg < NumMiscRegs);
398
399 const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
400 const auto &map = getMiscIndices(misc_reg);
401 int lower = map.first, upper = map.second;
402 // NB!: apply architectural masks according to desired register,

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410 if ((val & reg.res1()) != reg.res1()) {
411 DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n",
412 miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1());
413 }
414 return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao
415}
416
417

418MiscReg

418RegVal

419ISA::readMiscReg(int misc_reg, ThreadContext *tc)
420{
421 CPSR cpsr = 0;
422 PCState pc = 0;
423 SCR scr = 0;
424
425 if (misc_reg == MISCREG_CPSR) {
426 cpsr = miscRegs[misc_reg];

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465 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
466 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
467 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
468 // NB: Skipping the full loop, here
469 if (!nsacr.cp10) cpacrMask.cp10 = 0;
470 if (!nsacr.cp11) cpacrMask.cp11 = 0;
471 }
472 }

473 MiscReg val = readMiscRegNoEffect(MISCREG_CPACR);

473 RegVal val = readMiscRegNoEffect(MISCREG_CPACR);

474 val &= cpacrMask;
475 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n",
476 miscRegName[misc_reg], val);
477 return val;
478 }
479 case MISCREG_MPIDR:
480 case MISCREG_MPIDR_EL1:
481 return readMPIDR(system, tc);

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642 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
643 readMiscRegNoEffect(MISCREG_HCR_EL2),
644 readMiscRegNoEffect(MISCREG_CPSR),
645 readMiscRegNoEffect(MISCREG_SCR_EL3));
646 case MISCREG_DCZID_EL0:
647 return 0x04; // DC ZVA clear 64-byte chunks
648 case MISCREG_HCPTR:
649 {

650 MiscReg val = readMiscRegNoEffect(misc_reg);

650 RegVal val = readMiscRegNoEffect(misc_reg);

651 // The trap bit associated with CP14 is defined as RAZ
652 val &= ~(1 << 14);
653 // If a CP bit in NSACR is 0 then the corresponding bit in
654 // HCPTR is RAO/WI
655 bool secure_lookup = haveSecurity &&
656 inSecureState(readMiscRegNoEffect(MISCREG_SCR),
657 readMiscRegNoEffect(MISCREG_CPSR));
658 if (!secure_lookup) {

659 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR);

659 RegVal mask = readMiscRegNoEffect(MISCREG_NSACR);

660 val |= (mask ^ 0x7FFF) & 0xBFFF;
661 }
662 // Set the bits for unimplemented coprocessors to RAO/WI
663 val |= 0x33FF;
664 return (val);
665 }
666 case MISCREG_HDFAR: // alias for secure DFAR
667 return readMiscRegNoEffect(MISCREG_DFAR_S);

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705 default:
706 break;
707
708 }
709 return readMiscRegNoEffect(misc_reg);
710}
711
712void

713ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)

713ISA::setMiscRegNoEffect(int misc_reg, const RegVal &val)

714{
715 assert(misc_reg < NumMiscRegs);
716
717 const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
718 const auto &map = getMiscIndices(misc_reg);
719 int lower = map.first, upper = map.second;
720
721 auto v = (val & ~reg.wi()) | reg.rao();

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727 } else {
728 miscRegs[lower] = v;
729 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n",
730 misc_reg, lower, v);
731 }
732}
733
734void

735ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)

735ISA::setMiscReg(int misc_reg, const RegVal &val, ThreadContext *tc)

736{
737

738 MiscReg newVal = val;

738 RegVal newVal = val;

739 bool secure_lookup;
740 SCR scr;
741
742 if (misc_reg == MISCREG_CPSR) {
743 updateRegMap(val);
744
745
746 CPSR old_cpsr = miscRegs[MISCREG_CPSR];

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796 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
797 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
798 // NB: Skipping the full loop, here
799 if (!nsacr.cp10) cpacrMask.cp10 = 0;
800 if (!nsacr.cp11) cpacrMask.cp11 = 0;
801 }
802 }
803

804 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR);

804 RegVal old_val = readMiscRegNoEffect(MISCREG_CPACR);

805 newVal &= cpacrMask;
806 newVal |= old_val & ~cpacrMask;
807 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
808 miscRegName[misc_reg], newVal);
809 }
810 break;
811 case MISCREG_CPTR_EL2:
812 {

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989 sctlr_idx = MISCREG_SCTLR_S;
990 } else {
991 sctlr_idx = MISCREG_SCTLR_NS;
992 }
993
994 SCTLR sctlr = miscRegs[sctlr_idx];
995 SCTLR new_sctlr = newVal;
996 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization;

997 miscRegs[sctlr_idx] = (MiscReg)new_sctlr;

997 miscRegs[sctlr_idx] = (RegVal)new_sctlr;

998 getITBPtr(tc)->invalidateMiscReg();
999 getDTBPtr(tc)->invalidateMiscReg();
1000 }
1001 case MISCREG_MIDR:
1002 case MISCREG_ID_PFR0:
1003 case MISCREG_ID_PFR1:
1004 case MISCREG_ID_DFR0:
1005 case MISCREG_ID_MMFR0:

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1558 case MISCREG_HCPTR:
1559 {
1560 // If a CP bit in NSACR is 0 then the corresponding bit in
1561 // HCPTR is RAO/WI. Same applies to NSASEDIS
1562 secure_lookup = haveSecurity &&
1563 inSecureState(readMiscRegNoEffect(MISCREG_SCR),
1564 readMiscRegNoEffect(MISCREG_CPSR));
1565 if (!secure_lookup) {

1566 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR);
1567 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF;

1566 RegVal oldValue = readMiscRegNoEffect(MISCREG_HCPTR);
1567 RegVal mask =
1568 (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF;

1568 newVal = (newVal & ~mask) | (oldValue & mask);
1569 }
1570 break;
1571 }
1572 case MISCREG_HDFAR: // alias for secure DFAR
1573 misc_reg = MISCREG_DFAR_S;
1574 break;
1575 case MISCREG_HIFAR: // alias for secure IFAR

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1664 tc->pcState().pc(), tc->contextId());
1665
1666 fault = getDTBPtr(tc)->translateFunctional(
1667 req, tc, mode, tranType);
1668
1669 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1670 HCR hcr = readMiscRegNoEffect(MISCREG_HCR);
1671

1569 newVal = (newVal & ~mask) | (oldValue & mask);
1570 }
1571 break;
1572 }
1573 case MISCREG_HDFAR: // alias for secure DFAR
1574 misc_reg = MISCREG_DFAR_S;
1575 break;
1576 case MISCREG_HIFAR: // alias for secure IFAR

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1665 tc->pcState().pc(), tc->contextId());
1666
1667 fault = getDTBPtr(tc)->translateFunctional(
1668 req, tc, mode, tranType);
1669
1670 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1671 HCR hcr = readMiscRegNoEffect(MISCREG_HCR);
1672

1672 MiscReg newVal;

1673 RegVal newVal;

1673 if (fault == NoFault) {
1674 Addr paddr = req->getPaddr();
1675 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode ||
1676 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) {
1677 newVal = (paddr & mask(39, 12)) |
1678 (getDTBPtr(tc)->getAttr());
1679 } else {
1680 newVal = (paddr & 0xfffff000) |

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1918 miscRegName[misc_reg]);
1919
1920 req->setVirt(0, val, 0, flags, Request::funcMasterId,
1921 tc->pcState().pc());
1922 req->setContext(tc->contextId());
1923 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode,
1924 tranType);
1925

1674 if (fault == NoFault) {
1675 Addr paddr = req->getPaddr();
1676 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode ||
1677 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) {
1678 newVal = (paddr & mask(39, 12)) |
1679 (getDTBPtr(tc)->getAttr());
1680 } else {
1681 newVal = (paddr & 0xfffff000) |

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1919 miscRegName[misc_reg]);
1920
1921 req->setVirt(0, val, 0, flags, Request::funcMasterId,
1922 tc->pcState().pc());
1923 req->setContext(tc->contextId());
1924 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode,
1925 tranType);
1926

1926 MiscReg newVal;

1927 RegVal newVal;