isa.cc (13531:e6f1bf55d038) isa.cc (13549:307ffddbd819)
1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 1324 unchanged lines hidden (view full) ---

1333 case MISCREG_TLBI_ALLE3IS:
1334 {
1335 assert64(tc);
1336
1337 TLBIALL tlbiOp(EL3, true);
1338 tlbiOp.broadcast(tc);
1339 return;
1340 }
1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 1324 unchanged lines hidden (view full) ---

1333 case MISCREG_TLBI_ALLE3IS:
1334 {
1335 assert64(tc);
1336
1337 TLBIALL tlbiOp(EL3, true);
1338 tlbiOp.broadcast(tc);
1339 return;
1340 }
1341 // @todo: uncomment this to enable Virtualization
1342 // case MISCREG_TLBI_ALLE2IS:
1343 // case MISCREG_TLBI_ALLE2:
1341 // AArch64 TLB Invalidate All, EL2, Inner Shareable
1342 case MISCREG_TLBI_ALLE2:
1343 case MISCREG_TLBI_ALLE2IS:
1344 {
1345 assert64(tc);
1346 scr = readMiscReg(MISCREG_SCR, tc);
1347
1348 TLBIALL tlbiOp(EL2, haveSecurity && !scr.ns);
1349 tlbiOp(tc);
1350 return;
1351 }
1344 // AArch64 TLB Invalidate All, EL1
1345 case MISCREG_TLBI_ALLE1:
1346 case MISCREG_TLBI_VMALLE1:
1347 case MISCREG_TLBI_VMALLS12E1:
1348 // @todo: handle VMID and stage 2 to enable Virtualization
1349 {
1350 assert64(tc);
1351 scr = readMiscReg(MISCREG_SCR, tc);

--- 682 unchanged lines hidden --- 		1352 // AArch64 TLB Invalidate All, EL1
1353 case MISCREG_TLBI_ALLE1:
1354 case MISCREG_TLBI_VMALLE1:
1355 case MISCREG_TLBI_VMALLS12E1:
1356 // @todo: handle VMID and stage 2 to enable Virtualization
1357 {
1358 assert64(tc);
1359 scr = readMiscReg(MISCREG_SCR, tc);

--- 682 unchanged lines hidden ---