isa.cc (13173:210b6fc57533) isa.cc (13393:659fdbcd5722)
1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 110 unchanged lines hidden (view full) ---

119 initID32(p);
120
121 // We always initialize AArch64 ID registers even
122 // if we are in AArch32. This is done since if we
123 // are in SE mode we don't know if our ArmProcess is
124 // AArch32 or AArch64
125 initID64(p);
126
1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 110 unchanged lines hidden (view full) ---

119 initID32(p);
120
121 // We always initialize AArch64 ID registers even
122 // if we are in AArch32. This is done since if we
123 // are in SE mode we don't know if our ArmProcess is
124 // AArch32 or AArch64
125 initID64(p);
126
127 miscRegs[MISCREG_ID_ISAR5] = insertBits(
128 miscRegs[MISCREG_ID_ISAR5], 19, 4,
129 haveCrypto ? 0x1112 : 0x0);
130
131 if (FullSystem && system->highestELIs64()) {
132 // Initialize AArch64 state
133 clear64(p);
134 return;
135 }
136
137 // Initialize AArch32 state...
138
139 CPSR cpsr = 0;
140 cpsr.mode = MODE_USER;
141 miscRegs[MISCREG_CPSR] = cpsr;
142 updateRegMap(cpsr);
143
144 SCTLR sctlr = 0;
145 sctlr.te = (bool) sctlr_rst.te;
146 sctlr.nmfi = (bool) sctlr_rst.nmfi;
147 sctlr.v = (bool) sctlr_rst.v;
148 sctlr.u = 1;
149 sctlr.xp = 1;
150 sctlr.rao2 = 1;
151 sctlr.rao3 = 1;
152 sctlr.rao4 = 0xf; // SCTLR[6:3]
153 sctlr.uci = 1;
154 sctlr.dze = 1;
155 miscRegs[MISCREG_SCTLR_NS] = sctlr;
156 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
157 miscRegs[MISCREG_HCPTR] = 0;
158
159 // Start with an event in the mailbox
160 miscRegs[MISCREG_SEV_MAILBOX] = 1;
161
162 // Separate Instruction and Data TLBs
163 miscRegs[MISCREG_TLBTR] = 1;
164
165 MVFR0 mvfr0 = 0;
166 mvfr0.advSimdRegisters = 2;

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194 (2 << 14) | // 15:14
195 (0 << 12) | // 13:12
196 (2 << 10) | // 11:10
197 (2 << 8) | // 9:8
198 (2 << 6) | // 7:6
199 (2 << 4) | // 5:4
200 (1 << 2) | // 3:2
201 0; // 1:0
127 // Start with an event in the mailbox
128 miscRegs[MISCREG_SEV_MAILBOX] = 1;
129
130 // Separate Instruction and Data TLBs
131 miscRegs[MISCREG_TLBTR] = 1;
132
133 MVFR0 mvfr0 = 0;
134 mvfr0.advSimdRegisters = 2;

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162 (2 << 14) | // 15:14
163 (0 << 12) | // 13:12
164 (2 << 10) | // 11:10
165 (2 << 8) | // 9:8
166 (2 << 6) | // 7:6
167 (2 << 4) | // 5:4
168 (1 << 2) | // 3:2
169 0; // 1:0
170
202 miscRegs[MISCREG_NMRR_NS] =
203 (1 << 30) | // 31:30
204 (0 << 26) | // 27:26
205 (0 << 24) | // 25:24
206 (3 << 22) | // 23:22
207 (2 << 20) | // 21:20
208 (0 << 18) | // 19:18
209 (0 << 16) | // 17:16
210 (1 << 14) | // 15:14
211 (0 << 12) | // 13:12
212 (2 << 10) | // 11:10
213 (0 << 8) | // 9:8
214 (3 << 6) | // 7:6
215 (2 << 4) | // 5:4
216 (0 << 2) | // 3:2
217 0; // 1:0
218
171 miscRegs[MISCREG_NMRR_NS] =
172 (1 << 30) | // 31:30
173 (0 << 26) | // 27:26
174 (0 << 24) | // 25:24
175 (3 << 22) | // 23:22
176 (2 << 20) | // 21:20
177 (0 << 18) | // 19:18
178 (0 << 16) | // 17:16
179 (1 << 14) | // 15:14
180 (0 << 12) | // 13:12
181 (2 << 10) | // 11:10
182 (0 << 8) | // 9:8
183 (3 << 6) | // 7:6
184 (2 << 4) | // 5:4
185 (0 << 2) | // 3:2
186 0; // 1:0
187
188 if (FullSystem && system->highestELIs64()) {
189 // Initialize AArch64 state
190 clear64(p);
191 return;
192 }
193
194 // Initialize AArch32 state...
195 clear32(p, sctlr_rst);
196}
197
198void
199ISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst)
200{
201 CPSR cpsr = 0;
202 cpsr.mode = MODE_USER;
203
204 miscRegs[MISCREG_CPSR] = cpsr;
205 updateRegMap(cpsr);
206
207 SCTLR sctlr = 0;
208 sctlr.te = (bool) sctlr_rst.te;
209 sctlr.nmfi = (bool) sctlr_rst.nmfi;
210 sctlr.v = (bool) sctlr_rst.v;
211 sctlr.u = 1;
212 sctlr.xp = 1;
213 sctlr.rao2 = 1;
214 sctlr.rao3 = 1;
215 sctlr.rao4 = 0xf; // SCTLR[6:3]
216 sctlr.uci = 1;
217 sctlr.dze = 1;
218 miscRegs[MISCREG_SCTLR_NS] = sctlr;
219 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
220 miscRegs[MISCREG_HCPTR] = 0;
221
219 miscRegs[MISCREG_CPACR] = 0;
220
221 miscRegs[MISCREG_FPSID] = p->fpsid;
222
223 if (haveLPAE) {
224 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
225 ttbcr.eae = 0;
226 miscRegs[MISCREG_TTBCR_NS] = ttbcr;

--- 1770 unchanged lines hidden --- 		222 miscRegs[MISCREG_CPACR] = 0;
223
224 miscRegs[MISCREG_FPSID] = p->fpsid;
225
226 if (haveLPAE) {
227 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
228 ttbcr.eae = 0;
229 miscRegs[MISCREG_TTBCR_NS] = ttbcr;

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