isa.cc (12972:832a2d71a6cf) isa.cc (13114:777d445423d6)
1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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79
80 // Cache system-level properties
81 if (FullSystem && system) {
82 highestELIs64 = system->highestELIs64();
83 haveSecurity = system->haveSecurity();
84 haveLPAE = system->haveLPAE();
85 haveVirtualization = system->haveVirtualization();
86 haveLargeAsid64 = system->haveLargeAsid64();
1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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79
80 // Cache system-level properties
81 if (FullSystem && system) {
82 highestELIs64 = system->highestELIs64();
83 haveSecurity = system->haveSecurity();
84 haveLPAE = system->haveLPAE();
85 haveVirtualization = system->haveVirtualization();
86 haveLargeAsid64 = system->haveLargeAsid64();
87 physAddrRange64 = system->physAddrRange64();
87 physAddrRange = system->physAddrRange();
88 } else {
89 highestELIs64 = true; // ArmSystem::highestELIs64 does the same
90 haveSecurity = haveLPAE = haveVirtualization = false;
91 haveLargeAsid64 = false;
88 } else {
89 highestELIs64 = true; // ArmSystem::highestELIs64 does the same
90 haveSecurity = haveLPAE = haveVirtualization = false;
91 haveLargeAsid64 = false;
92 physAddrRange64 = 32; // dummy value
92 physAddrRange = 32; // dummy value
93 }
94
95 initializeMiscRegMetadata();
96 preUnflattenMiscReg();
97
98 clear();
99}
100

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109void
110ISA::clear()
111{
112 const Params *p(params());
113
114 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
115 memset(miscRegs, 0, sizeof(miscRegs));
116
93 }
94
95 initializeMiscRegMetadata();
96 preUnflattenMiscReg();
97
98 clear();
99}
100

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109void
110ISA::clear()
111{
112 const Params *p(params());
113
114 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
115 memset(miscRegs, 0, sizeof(miscRegs));
116
117 // Initialize configurable default values
118 miscRegs[MISCREG_MIDR] = p->midr;
119 miscRegs[MISCREG_MIDR_EL1] = p->midr;
120 miscRegs[MISCREG_VPIDR] = p->midr;
117 initID32(p);
121
118
122 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
123 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
124 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
125 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
126 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
127 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
119 // We always initialize AArch64 ID registers even
120 // if we are in AArch32. This is done since if we
121 // are in SE mode we don't know if our ArmProcess is
122 // AArch32 or AArch64
123 initID64(p);
128
124
129 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
130 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
131 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
132 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
133
134 if (FullSystem && system->highestELIs64()) {
135 // Initialize AArch64 state
136 clear64(p);
137 return;
138 }
139
140 // Initialize AArch32 state...
141

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285 // also MISCREG_SCTLR_EL2 (by mapping)
286 miscRegs[MISCREG_HSCTLR] = 0x30c50830;
287 } else {
288 // also MISCREG_SCTLR_EL1 (by mapping)
289 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init
290 // Always non-secure
291 miscRegs[MISCREG_SCR_EL3] = 1;
292 }
125 if (FullSystem && system->highestELIs64()) {
126 // Initialize AArch64 state
127 clear64(p);
128 return;
129 }
130
131 // Initialize AArch32 state...
132

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276 // also MISCREG_SCTLR_EL2 (by mapping)
277 miscRegs[MISCREG_HSCTLR] = 0x30c50830;
278 } else {
279 // also MISCREG_SCTLR_EL1 (by mapping)
280 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init
281 // Always non-secure
282 miscRegs[MISCREG_SCR_EL3] = 1;
283 }
284}
293
285
286void
287ISA::initID32(const ArmISAParams *p)
288{
289 // Initialize configurable default values
290 miscRegs[MISCREG_MIDR] = p->midr;
291 miscRegs[MISCREG_MIDR_EL1] = p->midr;
292 miscRegs[MISCREG_VPIDR] = p->midr;
293
294 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
295 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
296 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
297 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
298 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
299 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
300
301 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
302 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
303 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
304 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
305}
306
307void
308ISA::initID64(const ArmISAParams *p)
309{
294 // Initialize configurable id registers
295 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1;
296 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1;
297 miscRegs[MISCREG_ID_AA64DFR0_EL1] =
298 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
299 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3
300
301 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1;

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321 haveVirtualization ? 0x2 : 0x0);
322 // Large ASID support
323 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
324 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
325 haveLargeAsid64 ? 0x2 : 0x0);
326 // Physical address size
327 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
328 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
310 // Initialize configurable id registers
311 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1;
312 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1;
313 miscRegs[MISCREG_ID_AA64DFR0_EL1] =
314 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
315 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3
316
317 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1;

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337 haveVirtualization ? 0x2 : 0x0);
338 // Large ASID support
339 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
340 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
341 haveLargeAsid64 ? 0x2 : 0x0);
342 // Physical address size
343 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
344 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
329 encodePhysAddrRange64(physAddrRange64));
345 encodePhysAddrRange64(physAddrRange));
330}
331
332void
333ISA::startup(ThreadContext *tc)
334{
335 pmu->setThreadContext(tc);
336
337}

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347
348void
349ISA::startup(ThreadContext *tc)
350{
351 pmu->setThreadContext(tc);
352
353}

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