isa.cc (12675:f3439303feb4) isa.cc (12690:810dd3bdac8f)
1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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113 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
114 memset(miscRegs, 0, sizeof(miscRegs));
115
116 // Initialize configurable default values
117 miscRegs[MISCREG_MIDR] = p->midr;
118 miscRegs[MISCREG_MIDR_EL1] = p->midr;
119 miscRegs[MISCREG_VPIDR] = p->midr;
120
1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 104 unchanged lines hidden (view full) ---

113 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
114 memset(miscRegs, 0, sizeof(miscRegs));
115
116 // Initialize configurable default values
117 miscRegs[MISCREG_MIDR] = p->midr;
118 miscRegs[MISCREG_MIDR_EL1] = p->midr;
119 miscRegs[MISCREG_VPIDR] = p->midr;
120
121 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
122 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
123 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
124 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
125 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
126 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
127
128 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
129 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
130 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
131 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
132
121 if (FullSystem && system->highestELIs64()) {
122 // Initialize AArch64 state
123 clear64(p);
124 return;
125 }
126
127 // Initialize AArch32 state...
128

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203 (0 << 8) | // 9:8
204 (3 << 6) | // 7:6
205 (2 << 4) | // 5:4
206 (0 << 2) | // 3:2
207 0; // 1:0
208
209 miscRegs[MISCREG_CPACR] = 0;
210
133 if (FullSystem && system->highestELIs64()) {
134 // Initialize AArch64 state
135 clear64(p);
136 return;
137 }
138
139 // Initialize AArch32 state...
140

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215 (0 << 8) | // 9:8
216 (3 << 6) | // 7:6
217 (2 << 4) | // 5:4
218 (0 << 2) | // 3:2
219 0; // 1:0
220
221 miscRegs[MISCREG_CPACR] = 0;
222
211 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
212 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
213 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
214 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
215
216 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
217 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
218 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
219 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
220 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
221 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
222
223 miscRegs[MISCREG_FPSID] = p->fpsid;
224
225 if (haveLPAE) {
226 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
227 ttbcr.eae = 0;
228 miscRegs[MISCREG_TTBCR_NS] = ttbcr;
229 // Enforce consistency with system-level settings
230 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5;

--- 1717 unchanged lines hidden --- 		223 miscRegs[MISCREG_FPSID] = p->fpsid;
224
225 if (haveLPAE) {
226 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
227 ttbcr.eae = 0;
228 miscRegs[MISCREG_TTBCR_NS] = ttbcr;
229 // Enforce consistency with system-level settings
230 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5;

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