isa.cc (12671:2a9f13f15e91) | isa.cc (12675:f3439303feb4) |
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1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 1699 unchanged lines hidden (view full) --- 1708 case MISCREG_TCR_EL2: 1709 case MISCREG_TCR_EL3: 1710 case MISCREG_SCTLR_EL2: 1711 case MISCREG_SCTLR_EL3: 1712 case MISCREG_HSCTLR: 1713 case MISCREG_TTBR0_EL1: 1714 case MISCREG_TTBR1_EL1: 1715 case MISCREG_TTBR0_EL2: | 1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 1699 unchanged lines hidden (view full) --- 1708 case MISCREG_TCR_EL2: 1709 case MISCREG_TCR_EL3: 1710 case MISCREG_SCTLR_EL2: 1711 case MISCREG_SCTLR_EL3: 1712 case MISCREG_HSCTLR: 1713 case MISCREG_TTBR0_EL1: 1714 case MISCREG_TTBR1_EL1: 1715 case MISCREG_TTBR0_EL2: |
1716 case MISCREG_TTBR1_EL2: |
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1716 case MISCREG_TTBR0_EL3: 1717 getITBPtr(tc)->invalidateMiscReg(); 1718 getDTBPtr(tc)->invalidateMiscReg(); 1719 break; 1720 case MISCREG_NZCV: 1721 { 1722 CPSR cpsr = val; 1723 --- 223 unchanged lines hidden --- | 1717 case MISCREG_TTBR0_EL3: 1718 getITBPtr(tc)->invalidateMiscReg(); 1719 getDTBPtr(tc)->invalidateMiscReg(); 1720 break; 1721 case MISCREG_NZCV: 1722 { 1723 CPSR cpsr = val; 1724 --- 223 unchanged lines hidden --- |