isa.cc (12577:5cafe57f87e5) isa.cc (12604:0cf3d5d3bd3e)
1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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705
706} // anonymous namespace
707
708void
709ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
710{
711
712 MiscReg newVal = val;
1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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705
706} // anonymous namespace
707
708void
709ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
710{
711
712 MiscReg newVal = val;
713 int x;
714 bool secure_lookup;
715 bool hyp;
713 bool secure_lookup;
714 bool hyp;
716 System *sys;
717 ThreadContext *oc;
718 uint8_t target_el;
719 uint16_t asid;
720 SCR scr;
721
722 if (misc_reg == MISCREG_CPSR) {
723 updateRegMap(val);
724
725

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1024
1025 // TLBI all entries, EL0&1 inner sharable (ignored)
1026 case MISCREG_TLBIALLIS:
1027 case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
1028 assert32(tc);
1029 target_el = 1; // el 0 and 1 are handled together
1030 scr = readMiscReg(MISCREG_SCR, tc);
1031 secure_lookup = haveSecurity && !scr.ns;
715 uint8_t target_el;
716 uint16_t asid;
717 SCR scr;
718
719 if (misc_reg == MISCREG_CPSR) {
720 updateRegMap(val);
721
722

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1021
1022 // TLBI all entries, EL0&1 inner sharable (ignored)
1023 case MISCREG_TLBIALLIS:
1024 case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
1025 assert32(tc);
1026 target_el = 1; // el 0 and 1 are handled together
1027 scr = readMiscReg(MISCREG_SCR, tc);
1028 secure_lookup = haveSecurity && !scr.ns;
1032 sys = tc->getSystemPtr();
1033 for (x = 0; x < sys->numContexts(); x++) {
1034 oc = sys->getThreadContext(x);
1035 getITBPtr(oc)->flushAllSecurity(secure_lookup, target_el);
1036 getDTBPtr(oc)->flushAllSecurity(secure_lookup, target_el);
1037
1038 // If CheckerCPU is connected, need to notify it of a flush
1039 CheckerCPU *checker = oc->getCheckerCpuPtr();
1040 if (checker) {
1041 getITBPtr(checker)->flushAllSecurity(secure_lookup,
1042 target_el);
1043 getDTBPtr(checker)->flushAllSecurity(secure_lookup,
1044 target_el);
1045 }
1046 }
1029 tlbiALL(tc, secure_lookup, target_el);
1047 return;
1048 // TLBI all entries, EL0&1, instruction side
1049 case MISCREG_ITLBIALL:
1050 assert32(tc);
1051 target_el = 1; // el 0 and 1 are handled together
1052 scr = readMiscReg(MISCREG_SCR, tc);
1053 secure_lookup = haveSecurity && !scr.ns;
1054 getITBPtr(tc)->flushAllSecurity(secure_lookup, target_el);

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1068 // regardless of the level of lookup, since in gem5 we cache
1069 // in the tlb the last level of lookup only.
1070 case MISCREG_TLBIMVA:
1071 case MISCREG_TLBIMVAIS:
1072 assert32(tc);
1073 target_el = 1; // el 0 and 1 are handled together
1074 scr = readMiscReg(MISCREG_SCR, tc);
1075 secure_lookup = haveSecurity && !scr.ns;
1030 return;
1031 // TLBI all entries, EL0&1, instruction side
1032 case MISCREG_ITLBIALL:
1033 assert32(tc);
1034 target_el = 1; // el 0 and 1 are handled together
1035 scr = readMiscReg(MISCREG_SCR, tc);
1036 secure_lookup = haveSecurity && !scr.ns;
1037 getITBPtr(tc)->flushAllSecurity(secure_lookup, target_el);

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1051 // regardless of the level of lookup, since in gem5 we cache
1052 // in the tlb the last level of lookup only.
1053 case MISCREG_TLBIMVA:
1054 case MISCREG_TLBIMVAIS:
1055 assert32(tc);
1056 target_el = 1; // el 0 and 1 are handled together
1057 scr = readMiscReg(MISCREG_SCR, tc);
1058 secure_lookup = haveSecurity && !scr.ns;
1076 sys = tc->getSystemPtr();
1077 for (x = 0; x < sys->numContexts(); x++) {
1078 oc = sys->getThreadContext(x);
1079 getITBPtr(oc)->flushMvaAsid(mbits(newVal, 31, 12),
1080 bits(newVal, 7,0),
1081 secure_lookup, target_el);
1082 getDTBPtr(oc)->flushMvaAsid(mbits(newVal, 31, 12),
1083 bits(newVal, 7,0),
1084 secure_lookup, target_el);
1085
1086 CheckerCPU *checker = oc->getCheckerCpuPtr();
1087 if (checker) {
1088 getITBPtr(checker)->flushMvaAsid(mbits(newVal, 31, 12),
1089 bits(newVal, 7,0), secure_lookup, target_el);
1090 getDTBPtr(checker)->flushMvaAsid(mbits(newVal, 31, 12),
1091 bits(newVal, 7,0), secure_lookup, target_el);
1092 }
1093 }
1059 tlbiVA(tc, mbits(newVal, 31, 12), bits(newVal, 7,0),
1060 secure_lookup, target_el);
1094 return;
1095 // TLBI by ASID, EL0&1, inner sharable
1096 case MISCREG_TLBIASIDIS:
1097 case MISCREG_TLBIASID:
1098 assert32(tc);
1099 target_el = 1; // el 0 and 1 are handled together
1100 scr = readMiscReg(MISCREG_SCR, tc);
1101 secure_lookup = haveSecurity && !scr.ns;
1061 return;
1062 // TLBI by ASID, EL0&1, inner sharable
1063 case MISCREG_TLBIASIDIS:
1064 case MISCREG_TLBIASID:
1065 assert32(tc);
1066 target_el = 1; // el 0 and 1 are handled together
1067 scr = readMiscReg(MISCREG_SCR, tc);
1068 secure_lookup = haveSecurity && !scr.ns;
1102 sys = tc->getSystemPtr();
1103 for (x = 0; x < sys->numContexts(); x++) {
1104 oc = sys->getThreadContext(x);
1105 getITBPtr(oc)->flushAsid(bits(newVal, 7,0),
1106 secure_lookup, target_el);
1107 getDTBPtr(oc)->flushAsid(bits(newVal, 7,0),
1108 secure_lookup, target_el);
1109 CheckerCPU *checker = oc->getCheckerCpuPtr();
1110 if (checker) {
1111 getITBPtr(checker)->flushAsid(bits(newVal, 7,0),
1112 secure_lookup, target_el);
1113 getDTBPtr(checker)->flushAsid(bits(newVal, 7,0),
1114 secure_lookup, target_el);
1115 }
1116 }
1069 asid = bits(newVal, 7,0);
1070 tlbiASID(tc, asid, secure_lookup, target_el);
1117 return;
1118 // TLBI by address, EL0&1, inner sharable (ignored)
1119 case MISCREG_TLBIMVAAL:
1120 case MISCREG_TLBIMVAALIS:
1121 // mcr tlbimvaal(is) is invalidating all matching entries
1122 // regardless of the level of lookup, since in gem5 we cache
1123 // in the tlb the last level of lookup only.
1124 case MISCREG_TLBIMVAA:
1125 case MISCREG_TLBIMVAAIS:
1126 assert32(tc);
1127 target_el = 1; // el 0 and 1 are handled together
1128 scr = readMiscReg(MISCREG_SCR, tc);
1129 secure_lookup = haveSecurity && !scr.ns;
1130 hyp = 0;
1071 return;
1072 // TLBI by address, EL0&1, inner sharable (ignored)
1073 case MISCREG_TLBIMVAAL:
1074 case MISCREG_TLBIMVAALIS:
1075 // mcr tlbimvaal(is) is invalidating all matching entries
1076 // regardless of the level of lookup, since in gem5 we cache
1077 // in the tlb the last level of lookup only.
1078 case MISCREG_TLBIMVAA:
1079 case MISCREG_TLBIMVAAIS:
1080 assert32(tc);
1081 target_el = 1; // el 0 and 1 are handled together
1082 scr = readMiscReg(MISCREG_SCR, tc);
1083 secure_lookup = haveSecurity && !scr.ns;
1084 hyp = 0;
1131 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el);
1085 tlbiMVA(tc, mbits(newVal, 31,12), secure_lookup, hyp, target_el);
1132 return;
1133 // TLBI by address, EL2, hypervisor mode
1134 case MISCREG_TLBIMVALH:
1135 case MISCREG_TLBIMVALHIS:
1136 // mcr tlbimvalh(is) is invalidating all matching entries
1137 // regardless of the level of lookup, since in gem5 we cache
1138 // in the tlb the last level of lookup only.
1139 case MISCREG_TLBIMVAH:
1140 case MISCREG_TLBIMVAHIS:
1141 assert32(tc);
1142 target_el = 1; // aarch32, use hyp bit
1143 scr = readMiscReg(MISCREG_SCR, tc);
1144 secure_lookup = haveSecurity && !scr.ns;
1145 hyp = 1;
1086 return;
1087 // TLBI by address, EL2, hypervisor mode
1088 case MISCREG_TLBIMVALH:
1089 case MISCREG_TLBIMVALHIS:
1090 // mcr tlbimvalh(is) is invalidating all matching entries
1091 // regardless of the level of lookup, since in gem5 we cache
1092 // in the tlb the last level of lookup only.
1093 case MISCREG_TLBIMVAH:
1094 case MISCREG_TLBIMVAHIS:
1095 assert32(tc);
1096 target_el = 1; // aarch32, use hyp bit
1097 scr = readMiscReg(MISCREG_SCR, tc);
1098 secure_lookup = haveSecurity && !scr.ns;
1099 hyp = 1;
1146 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el);
1100 tlbiMVA(tc, mbits(newVal, 31,12), secure_lookup, hyp, target_el);
1147 return;
1148 case MISCREG_TLBIIPAS2L:
1149 case MISCREG_TLBIIPAS2LIS:
1150 // mcr tlbiipas2l(is) is invalidating all matching entries
1151 // regardless of the level of lookup, since in gem5 we cache
1152 // in the tlb the last level of lookup only.
1153 case MISCREG_TLBIIPAS2:
1154 case MISCREG_TLBIIPAS2IS:

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1246 case MISCREG_TLBI_VAE3_Xt:
1247 // TLBI by VA, EL3 regime stage 1, last level walk
1248 case MISCREG_TLBI_VALE3IS_Xt:
1249 case MISCREG_TLBI_VALE3_Xt:
1250 assert64(tc);
1251 target_el = 3;
1252 asid = 0xbeef; // does not matter, tlbi is global
1253 secure_lookup = true;
1101 return;
1102 case MISCREG_TLBIIPAS2L:
1103 case MISCREG_TLBIIPAS2LIS:
1104 // mcr tlbiipas2l(is) is invalidating all matching entries
1105 // regardless of the level of lookup, since in gem5 we cache
1106 // in the tlb the last level of lookup only.
1107 case MISCREG_TLBIIPAS2:
1108 case MISCREG_TLBIIPAS2IS:

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1200 case MISCREG_TLBI_VAE3_Xt:
1201 // TLBI by VA, EL3 regime stage 1, last level walk
1202 case MISCREG_TLBI_VALE3IS_Xt:
1203 case MISCREG_TLBI_VALE3_Xt:
1204 assert64(tc);
1205 target_el = 3;
1206 asid = 0xbeef; // does not matter, tlbi is global
1207 secure_lookup = true;
1254 tlbiVA(tc, newVal, asid, secure_lookup, target_el);
1208 tlbiVA(tc, ((Addr) bits(newVal, 43, 0)) << 12,
1209 asid, secure_lookup, target_el);
1255 return;
1256 // TLBI by VA, EL2
1257 case MISCREG_TLBI_VAE2IS_Xt:
1258 case MISCREG_TLBI_VAE2_Xt:
1259 // TLBI by VA, EL2, stage1 last level walk
1260 case MISCREG_TLBI_VALE2IS_Xt:
1261 case MISCREG_TLBI_VALE2_Xt:
1262 assert64(tc);
1263 target_el = 2;
1264 asid = 0xbeef; // does not matter, tlbi is global
1265 scr = readMiscReg(MISCREG_SCR, tc);
1266 secure_lookup = haveSecurity && !scr.ns;
1210 return;
1211 // TLBI by VA, EL2
1212 case MISCREG_TLBI_VAE2IS_Xt:
1213 case MISCREG_TLBI_VAE2_Xt:
1214 // TLBI by VA, EL2, stage1 last level walk
1215 case MISCREG_TLBI_VALE2IS_Xt:
1216 case MISCREG_TLBI_VALE2_Xt:
1217 assert64(tc);
1218 target_el = 2;
1219 asid = 0xbeef; // does not matter, tlbi is global
1220 scr = readMiscReg(MISCREG_SCR, tc);
1221 secure_lookup = haveSecurity && !scr.ns;
1267 tlbiVA(tc, newVal, asid, secure_lookup, target_el);
1222 tlbiVA(tc, ((Addr) bits(newVal, 43, 0)) << 12,
1223 asid, secure_lookup, target_el);
1268 return;
1269 // TLBI by VA EL1 & 0, stage1, ASID, current VMID
1270 case MISCREG_TLBI_VAE1IS_Xt:
1271 case MISCREG_TLBI_VAE1_Xt:
1272 case MISCREG_TLBI_VALE1IS_Xt:
1273 case MISCREG_TLBI_VALE1_Xt:
1274 assert64(tc);
1275 asid = bits(newVal, 63, 48);
1276 target_el = 1; // el 0 and 1 are handled together
1277 scr = readMiscReg(MISCREG_SCR, tc);
1278 secure_lookup = haveSecurity && !scr.ns;
1224 return;
1225 // TLBI by VA EL1 & 0, stage1, ASID, current VMID
1226 case MISCREG_TLBI_VAE1IS_Xt:
1227 case MISCREG_TLBI_VAE1_Xt:
1228 case MISCREG_TLBI_VALE1IS_Xt:
1229 case MISCREG_TLBI_VALE1_Xt:
1230 assert64(tc);
1231 asid = bits(newVal, 63, 48);
1232 target_el = 1; // el 0 and 1 are handled together
1233 scr = readMiscReg(MISCREG_SCR, tc);
1234 secure_lookup = haveSecurity && !scr.ns;
1279 tlbiVA(tc, newVal, asid, secure_lookup, target_el);
1235 tlbiVA(tc, ((Addr) bits(newVal, 43, 0)) << 12,
1236 asid, secure_lookup, target_el);
1280 return;
1281 // AArch64 TLBI: invalidate by ASID, stage 1, current VMID
1282 // @todo: handle VMID to enable Virtualization
1283 case MISCREG_TLBI_ASIDE1IS_Xt:
1284 case MISCREG_TLBI_ASIDE1_Xt:
1285 assert64(tc);
1286 target_el = 1; // el 0 and 1 are handled together
1287 scr = readMiscReg(MISCREG_SCR, tc);
1288 secure_lookup = haveSecurity && !scr.ns;
1237 return;
1238 // AArch64 TLBI: invalidate by ASID, stage 1, current VMID
1239 // @todo: handle VMID to enable Virtualization
1240 case MISCREG_TLBI_ASIDE1IS_Xt:
1241 case MISCREG_TLBI_ASIDE1_Xt:
1242 assert64(tc);
1243 target_el = 1; // el 0 and 1 are handled together
1244 scr = readMiscReg(MISCREG_SCR, tc);
1245 secure_lookup = haveSecurity && !scr.ns;
1289 sys = tc->getSystemPtr();
1290 for (x = 0; x < sys->numContexts(); x++) {
1291 oc = sys->getThreadContext(x);
1292 asid = bits(newVal, 63, 48);
1293 if (!haveLargeAsid64)
1294 asid &= mask(8);
1295 getITBPtr(oc)->flushAsid(asid, secure_lookup, target_el);
1296 getDTBPtr(oc)->flushAsid(asid, secure_lookup, target_el);
1297 CheckerCPU *checker = oc->getCheckerCpuPtr();
1298 if (checker) {
1299 getITBPtr(checker)->flushAsid(asid,
1300 secure_lookup, target_el);
1301 getDTBPtr(checker)->flushAsid(asid,
1302 secure_lookup, target_el);
1303 }
1304 }
1246 asid = bits(newVal, 63, 48);
1247 tlbiASID(tc, asid, secure_lookup, target_el);
1305 return;
1306 // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID
1307 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1308 // entries from the last level of translation table walks
1309 // @todo: handle VMID to enable Virtualization
1310 case MISCREG_TLBI_VAAE1IS_Xt:
1311 case MISCREG_TLBI_VAAE1_Xt:
1312 case MISCREG_TLBI_VAALE1IS_Xt:
1313 case MISCREG_TLBI_VAALE1_Xt:
1314 assert64(tc);
1315 target_el = 1; // el 0 and 1 are handled together
1316 scr = readMiscReg(MISCREG_SCR, tc);
1317 secure_lookup = haveSecurity && !scr.ns;
1248 return;
1249 // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID
1250 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1251 // entries from the last level of translation table walks
1252 // @todo: handle VMID to enable Virtualization
1253 case MISCREG_TLBI_VAAE1IS_Xt:
1254 case MISCREG_TLBI_VAAE1_Xt:
1255 case MISCREG_TLBI_VAALE1IS_Xt:
1256 case MISCREG_TLBI_VAALE1_Xt:
1257 assert64(tc);
1258 target_el = 1; // el 0 and 1 are handled together
1259 scr = readMiscReg(MISCREG_SCR, tc);
1260 secure_lookup = haveSecurity && !scr.ns;
1318 sys = tc->getSystemPtr();
1319 for (x = 0; x < sys->numContexts(); x++) {
1320 // @todo: extra controls on TLBI broadcast?
1321 oc = sys->getThreadContext(x);
1322 Addr va = ((Addr) bits(newVal, 43, 0)) << 12;
1323 getITBPtr(oc)->flushMva(va,
1261 tlbiMVA(tc,
1262 ((Addr)bits(newVal, 43, 0)) << 12,
1324 secure_lookup, false, target_el);
1263 secure_lookup, false, target_el);
1325 getDTBPtr(oc)->flushMva(va,
1326 secure_lookup, false, target_el);
1327
1328 CheckerCPU *checker = oc->getCheckerCpuPtr();
1329 if (checker) {
1330 getITBPtr(checker)->flushMva(va,
1331 secure_lookup, false, target_el);
1332 getDTBPtr(checker)->flushMva(va,
1333 secure_lookup, false, target_el);
1334 }
1335 }
1336 return;
1337 // AArch64 TLBI: invalidate by IPA, stage 2, current VMID
1338 case MISCREG_TLBI_IPAS2LE1IS_Xt:
1339 case MISCREG_TLBI_IPAS2LE1_Xt:
1340 case MISCREG_TLBI_IPAS2E1IS_Xt:
1341 case MISCREG_TLBI_IPAS2E1_Xt:
1342 assert64(tc);
1343 target_el = 1; // EL 0 and 1 are handled together

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1786 getGenericTimer(tc).setMiscReg(misc_reg, newVal);
1787 break;
1788 }
1789 }
1790 setMiscRegNoEffect(misc_reg, newVal);
1791}
1792
1793void
1264 return;
1265 // AArch64 TLBI: invalidate by IPA, stage 2, current VMID
1266 case MISCREG_TLBI_IPAS2LE1IS_Xt:
1267 case MISCREG_TLBI_IPAS2LE1_Xt:
1268 case MISCREG_TLBI_IPAS2E1IS_Xt:
1269 case MISCREG_TLBI_IPAS2E1_Xt:
1270 assert64(tc);
1271 target_el = 1; // EL 0 and 1 are handled together

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1714 getGenericTimer(tc).setMiscReg(misc_reg, newVal);
1715 break;
1716 }
1717 }
1718 setMiscRegNoEffect(misc_reg, newVal);
1719}
1720
1721void
1794ISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid,
1722ISA::tlbiVA(ThreadContext *tc, Addr va, uint16_t asid,
1795 bool secure_lookup, uint8_t target_el)
1796{
1797 if (!haveLargeAsid64)
1798 asid &= mask(8);
1723 bool secure_lookup, uint8_t target_el)
1724{
1725 if (!haveLargeAsid64)
1726 asid &= mask(8);
1799 Addr va = ((Addr) bits(newVal, 43, 0)) << 12;
1800 System *sys = tc->getSystemPtr();
1801 for (int x = 0; x < sys->numContexts(); x++) {
1802 ThreadContext *oc = sys->getThreadContext(x);
1803 getITBPtr(oc)->flushMvaAsid(va, asid,
1804 secure_lookup, target_el);
1805 getDTBPtr(oc)->flushMvaAsid(va, asid,
1806 secure_lookup, target_el);
1807

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1848 if (checker) {
1849 getITBPtr(checker)->flushAllNs(hyp, target_el);
1850 getDTBPtr(checker)->flushAllNs(hyp, target_el);
1851 }
1852 }
1853}
1854
1855void
1727 System *sys = tc->getSystemPtr();
1728 for (int x = 0; x < sys->numContexts(); x++) {
1729 ThreadContext *oc = sys->getThreadContext(x);
1730 getITBPtr(oc)->flushMvaAsid(va, asid,
1731 secure_lookup, target_el);
1732 getDTBPtr(oc)->flushMvaAsid(va, asid,
1733 secure_lookup, target_el);
1734

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1775 if (checker) {
1776 getITBPtr(checker)->flushAllNs(hyp, target_el);
1777 getDTBPtr(checker)->flushAllNs(hyp, target_el);
1778 }
1779 }
1780}
1781
1782void
1856ISA::tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp,
1783ISA::tlbiMVA(ThreadContext *tc, Addr va, bool secure_lookup, bool hyp,
1857 uint8_t target_el)
1858{
1859 System *sys = tc->getSystemPtr();
1860 for (int x = 0; x < sys->numContexts(); x++) {
1861 ThreadContext *oc = sys->getThreadContext(x);
1784 uint8_t target_el)
1785{
1786 System *sys = tc->getSystemPtr();
1787 for (int x = 0; x < sys->numContexts(); x++) {
1788 ThreadContext *oc = sys->getThreadContext(x);
1862 getITBPtr(oc)->flushMva(mbits(newVal, 31,12),
1863 secure_lookup, hyp, target_el);
1864 getDTBPtr(oc)->flushMva(mbits(newVal, 31,12),
1865 secure_lookup, hyp, target_el);
1789 getITBPtr(oc)->flushMva(va, secure_lookup, hyp, target_el);
1790 getDTBPtr(oc)->flushMva(va, secure_lookup, hyp, target_el);
1866
1867 CheckerCPU *checker = oc->getCheckerCpuPtr();
1868 if (checker) {
1791
1792 CheckerCPU *checker = oc->getCheckerCpuPtr();
1793 if (checker) {
1869 getITBPtr(checker)->flushMva(mbits(newVal, 31,12),
1870 secure_lookup, hyp, target_el);
1871 getDTBPtr(checker)->flushMva(mbits(newVal, 31,12),
1872 secure_lookup, hyp, target_el);
1794 getITBPtr(checker)->flushMva(va, secure_lookup, hyp, target_el);
1795 getDTBPtr(checker)->flushMva(va, secure_lookup, hyp, target_el);
1873 }
1874 }
1875}
1876
1877void
1878ISA::tlbiIPA(ThreadContext *tc, MiscReg newVal, bool secure_lookup,
1879 uint8_t target_el)
1880{

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1892 getITBPtr(checker)->flushIpaVmid(ipa,
1893 secure_lookup, false, target_el);
1894 getDTBPtr(checker)->flushIpaVmid(ipa,
1895 secure_lookup, false, target_el);
1896 }
1897 }
1898}
1899
1796 }
1797 }
1798}
1799
1800void
1801ISA::tlbiIPA(ThreadContext *tc, MiscReg newVal, bool secure_lookup,
1802 uint8_t target_el)
1803{

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1815 getITBPtr(checker)->flushIpaVmid(ipa,
1816 secure_lookup, false, target_el);
1817 getDTBPtr(checker)->flushIpaVmid(ipa,
1818 secure_lookup, false, target_el);
1819 }
1820 }
1821}
1822
1823void
1824ISA::tlbiASID(ThreadContext *tc, uint16_t asid, bool secure_lookup,
1825 uint8_t target_el)
1826{
1827 if (!haveLargeAsid64)
1828 asid &= mask(8);
1829
1830 System *sys = tc->getSystemPtr();
1831 for (auto x = 0; x < sys->numContexts(); x++) {
1832 tc = sys->getThreadContext(x);
1833 getITBPtr(tc)->flushAsid(asid, secure_lookup, target_el);
1834 getDTBPtr(tc)->flushAsid(asid, secure_lookup, target_el);
1835 CheckerCPU *checker = tc->getCheckerCpuPtr();
1836 if (checker) {
1837 getITBPtr(checker)->flushAsid(asid, secure_lookup, target_el);
1838 getDTBPtr(checker)->flushAsid(asid, secure_lookup, target_el);
1839 }
1840 }
1841}
1842
1900BaseISADevice &
1901ISA::getGenericTimer(ThreadContext *tc)
1902{
1903 // We only need to create an ISA interface the first time we try
1904 // to access the timer.
1905 if (timer)
1906 return *timer.get();
1907

--- 18 unchanged lines hidden --- 		1843BaseISADevice &
1844ISA::getGenericTimer(ThreadContext *tc)
1845{
1846 // We only need to create an ISA interface the first time we try
1847 // to access the timer.
1848 if (timer)
1849 return *timer.get();
1850

--- 18 unchanged lines hidden ---