isa.cc (12576:e55d2103ccac) isa.cc (12577:5cafe57f87e5)
1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1140 case MISCREG_TLBIMVAHIS:
1141 assert32(tc);
1142 target_el = 1; // aarch32, use hyp bit
1143 scr = readMiscReg(MISCREG_SCR, tc);
1144 secure_lookup = haveSecurity && !scr.ns;
1145 hyp = 1;
1146 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el);
1147 return;
1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1140 case MISCREG_TLBIMVAHIS:
1141 assert32(tc);
1142 target_el = 1; // aarch32, use hyp bit
1143 scr = readMiscReg(MISCREG_SCR, tc);
1144 secure_lookup = haveSecurity && !scr.ns;
1145 hyp = 1;
1146 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el);
1147 return;
1148 case MISCREG_TLBIIPAS2L:
1149 case MISCREG_TLBIIPAS2LIS:
1150 // mcr tlbiipas2l(is) is invalidating all matching entries
1151 // regardless of the level of lookup, since in gem5 we cache
1152 // in the tlb the last level of lookup only.
1153 case MISCREG_TLBIIPAS2:
1154 case MISCREG_TLBIIPAS2IS:
1155 assert32(tc);
1156 target_el = 1; // EL 0 and 1 are handled together
1157 scr = readMiscReg(MISCREG_SCR, tc);
1158 secure_lookup = haveSecurity && !scr.ns;
1159 tlbiIPA(tc, newVal, secure_lookup, target_el);
1160 return;
1148 // TLBI by address and asid, EL0&1, instruction side only
1149 case MISCREG_ITLBIMVA:
1150 assert32(tc);
1151 target_el = 1; // el 0 and 1 are handled together
1152 scr = readMiscReg(MISCREG_SCR, tc);
1153 secure_lookup = haveSecurity && !scr.ns;
1154 getITBPtr(tc)->flushMvaAsid(mbits(newVal, 31, 12),
1155 bits(newVal, 7,0), secure_lookup, target_el);

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1325 case MISCREG_TLBI_IPAS2LE1IS_Xt:
1326 case MISCREG_TLBI_IPAS2LE1_Xt:
1327 case MISCREG_TLBI_IPAS2E1IS_Xt:
1328 case MISCREG_TLBI_IPAS2E1_Xt:
1329 assert64(tc);
1330 target_el = 1; // EL 0 and 1 are handled together
1331 scr = readMiscReg(MISCREG_SCR, tc);
1332 secure_lookup = haveSecurity && !scr.ns;
1161 // TLBI by address and asid, EL0&1, instruction side only
1162 case MISCREG_ITLBIMVA:
1163 assert32(tc);
1164 target_el = 1; // el 0 and 1 are handled together
1165 scr = readMiscReg(MISCREG_SCR, tc);
1166 secure_lookup = haveSecurity && !scr.ns;
1167 getITBPtr(tc)->flushMvaAsid(mbits(newVal, 31, 12),
1168 bits(newVal, 7,0), secure_lookup, target_el);

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1338 case MISCREG_TLBI_IPAS2LE1IS_Xt:
1339 case MISCREG_TLBI_IPAS2LE1_Xt:
1340 case MISCREG_TLBI_IPAS2E1IS_Xt:
1341 case MISCREG_TLBI_IPAS2E1_Xt:
1342 assert64(tc);
1343 target_el = 1; // EL 0 and 1 are handled together
1344 scr = readMiscReg(MISCREG_SCR, tc);
1345 secure_lookup = haveSecurity && !scr.ns;
1333 sys = tc->getSystemPtr();
1334 for (x = 0; x < sys->numContexts(); x++) {
1335 oc = sys->getThreadContext(x);
1336 Addr ipa = ((Addr) bits(newVal, 35, 0)) << 12;
1337 getITBPtr(oc)->flushIpaVmid(ipa,
1338 secure_lookup, false, target_el);
1339 getDTBPtr(oc)->flushIpaVmid(ipa,
1340 secure_lookup, false, target_el);
1341
1342 CheckerCPU *checker = oc->getCheckerCpuPtr();
1343 if (checker) {
1344 getITBPtr(checker)->flushIpaVmid(ipa,
1345 secure_lookup, false, target_el);
1346 getDTBPtr(checker)->flushIpaVmid(ipa,
1347 secure_lookup, false, target_el);
1348 }
1349 }
1346 tlbiIPA(tc, newVal, secure_lookup, target_el);
1350 return;
1351 case MISCREG_ACTLR:
1352 warn("Not doing anything for write of miscreg ACTLR\n");
1353 break;
1354
1355 case MISCREG_PMXEVTYPER_PMCCFILTR:
1356 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
1357 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:

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1872 getITBPtr(checker)->flushMva(mbits(newVal, 31,12),
1873 secure_lookup, hyp, target_el);
1874 getDTBPtr(checker)->flushMva(mbits(newVal, 31,12),
1875 secure_lookup, hyp, target_el);
1876 }
1877 }
1878}
1879
1347 return;
1348 case MISCREG_ACTLR:
1349 warn("Not doing anything for write of miscreg ACTLR\n");
1350 break;
1351
1352 case MISCREG_PMXEVTYPER_PMCCFILTR:
1353 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
1354 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:

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1869 getITBPtr(checker)->flushMva(mbits(newVal, 31,12),
1870 secure_lookup, hyp, target_el);
1871 getDTBPtr(checker)->flushMva(mbits(newVal, 31,12),
1872 secure_lookup, hyp, target_el);
1873 }
1874 }
1875}
1876
1877void
1878ISA::tlbiIPA(ThreadContext *tc, MiscReg newVal, bool secure_lookup,
1879 uint8_t target_el)
1880{
1881 System *sys = tc->getSystemPtr();
1882 for (auto x = 0; x < sys->numContexts(); x++) {
1883 tc = sys->getThreadContext(x);
1884 Addr ipa = ((Addr) bits(newVal, 35, 0)) << 12;
1885 getITBPtr(tc)->flushIpaVmid(ipa,
1886 secure_lookup, false, target_el);
1887 getDTBPtr(tc)->flushIpaVmid(ipa,
1888 secure_lookup, false, target_el);
1889
1890 CheckerCPU *checker = tc->getCheckerCpuPtr();
1891 if (checker) {
1892 getITBPtr(checker)->flushIpaVmid(ipa,
1893 secure_lookup, false, target_el);
1894 getDTBPtr(checker)->flushIpaVmid(ipa,
1895 secure_lookup, false, target_el);
1896 }
1897 }
1898}
1899
1880BaseISADevice &
1881ISA::getGenericTimer(ThreadContext *tc)
1882{
1883 // We only need to create an ISA interface the first time we try
1884 // to access the timer.
1885 if (timer)
1886 return *timer.get();
1887

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1901ISA::getGenericTimer(ThreadContext *tc)
1902{
1903 // We only need to create an ISA interface the first time we try
1904 // to access the timer.
1905 if (timer)
1906 return *timer.get();
1907

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