isa.cc (12478:604310e2d7ad) isa.cc (12479:c686e4a1fe8f)
1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 41 unchanged lines hidden (view full) ---

50#include "params/ArmISA.hh"
51#include "sim/faults.hh"
52#include "sim/stat_control.hh"
53#include "sim/system.hh"
54
55namespace ArmISA
56{
57
1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 41 unchanged lines hidden (view full) ---

50#include "params/ArmISA.hh"
51#include "sim/faults.hh"
52#include "sim/stat_control.hh"
53#include "sim/system.hh"
54
55namespace ArmISA
56{
57
58
59/**
60 * Some registers alias with others, and therefore need to be translated.
61 * When two mapping registers are given, they are the 32b lower and
62 * upper halves, respectively, of the 64b register being mapped.
63 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
64 */
65void
66ISA::initializeMiscRegMetadata()
67{
68 InitReg(MISCREG_ACTLR_EL1).mapsTo(MISCREG_ACTLR_NS);
69 InitReg(MISCREG_AFSR0_EL1).mapsTo(MISCREG_ADFSR_NS);
70 InitReg(MISCREG_AFSR1_EL1).mapsTo(MISCREG_AIFSR_NS);
71 InitReg(MISCREG_AMAIR_EL1).mapsTo(MISCREG_AMAIR0_NS,
72 MISCREG_AMAIR1_NS);
73 InitReg(MISCREG_CONTEXTIDR_EL1).mapsTo(MISCREG_CONTEXTIDR_NS);
74 InitReg(MISCREG_CPACR_EL1).mapsTo(MISCREG_CPACR);
75 InitReg(MISCREG_CSSELR_EL1).mapsTo(MISCREG_CSSELR_NS);
76 InitReg(MISCREG_DACR32_EL2).mapsTo(MISCREG_DACR_NS);
77 InitReg(MISCREG_FAR_EL1).mapsTo(MISCREG_DFAR_NS,
78 MISCREG_IFAR_NS);
79 // ESR_EL1 -> DFSR
80 InitReg(MISCREG_HACR_EL2).mapsTo(MISCREG_HACR);
81 InitReg(MISCREG_ACTLR_EL2).mapsTo(MISCREG_HACTLR);
82 InitReg(MISCREG_AFSR0_EL2).mapsTo(MISCREG_HADFSR);
83 InitReg(MISCREG_AFSR1_EL2).mapsTo(MISCREG_HAIFSR);
84 InitReg(MISCREG_AMAIR_EL2).mapsTo(MISCREG_HAMAIR0,
85 MISCREG_HAMAIR1);
86 InitReg(MISCREG_CPTR_EL2).mapsTo(MISCREG_HCPTR);
87 InitReg(MISCREG_HCR_EL2).mapsTo(MISCREG_HCR /*,
88 MISCREG_HCR2*/);
89 InitReg(MISCREG_MDCR_EL2).mapsTo(MISCREG_HDCR);
90 InitReg(MISCREG_FAR_EL2).mapsTo(MISCREG_HDFAR,
91 MISCREG_HIFAR);
92 InitReg(MISCREG_MAIR_EL2).mapsTo(MISCREG_HMAIR0,
93 MISCREG_HMAIR1);
94 InitReg(MISCREG_HPFAR_EL2).mapsTo(MISCREG_HPFAR);
95 InitReg(MISCREG_SCTLR_EL2).mapsTo(MISCREG_HSCTLR);
96 InitReg(MISCREG_ESR_EL2).mapsTo(MISCREG_HSR);
97 InitReg(MISCREG_HSTR_EL2).mapsTo(MISCREG_HSTR);
98 InitReg(MISCREG_TCR_EL2).mapsTo(MISCREG_HTCR);
99 InitReg(MISCREG_TPIDR_EL2).mapsTo(MISCREG_HTPIDR);
100 InitReg(MISCREG_TTBR0_EL2).mapsTo(MISCREG_HTTBR);
101 InitReg(MISCREG_VBAR_EL2).mapsTo(MISCREG_HVBAR);
102 InitReg(MISCREG_IFSR32_EL2).mapsTo(MISCREG_IFSR_NS);
103 InitReg(MISCREG_MAIR_EL1).mapsTo(MISCREG_PRRR_NS,
104 MISCREG_NMRR_NS);
105 InitReg(MISCREG_PAR_EL1).mapsTo(MISCREG_PAR_NS);
106 // RMR_EL1 -> RMR
107 // RMR_EL2 -> HRMR
108 InitReg(MISCREG_SCTLR_EL1).mapsTo(MISCREG_SCTLR_NS);
109 InitReg(MISCREG_SDER32_EL3).mapsTo(MISCREG_SDER);
110 InitReg(MISCREG_TPIDR_EL1).mapsTo(MISCREG_TPIDRPRW_NS);
111 InitReg(MISCREG_TPIDRRO_EL0).mapsTo(MISCREG_TPIDRURO_NS);
112 InitReg(MISCREG_TPIDR_EL0).mapsTo(MISCREG_TPIDRURW_NS);
113 InitReg(MISCREG_TCR_EL1).mapsTo(MISCREG_TTBCR_NS);
114 InitReg(MISCREG_TTBR0_EL1).mapsTo(MISCREG_TTBR0_NS);
115 InitReg(MISCREG_TTBR1_EL1).mapsTo(MISCREG_TTBR1_NS);
116 InitReg(MISCREG_VBAR_EL1).mapsTo(MISCREG_VBAR_NS);
117 InitReg(MISCREG_VMPIDR_EL2).mapsTo(MISCREG_VMPIDR);
118 InitReg(MISCREG_VPIDR_EL2).mapsTo(MISCREG_VPIDR);
119 InitReg(MISCREG_VTCR_EL2).mapsTo(MISCREG_VTCR);
120 InitReg(MISCREG_VTTBR_EL2).mapsTo(MISCREG_VTTBR);
121 InitReg(MISCREG_CNTFRQ_EL0).mapsTo(MISCREG_CNTFRQ);
122 InitReg(MISCREG_CNTHCTL_EL2).mapsTo(MISCREG_CNTHCTL);
123 InitReg(MISCREG_CNTHP_CTL_EL2).mapsTo(MISCREG_CNTHP_CTL);
124 InitReg(MISCREG_CNTHP_CVAL_EL2).mapsTo(MISCREG_CNTHP_CVAL); /* 64b */
125 InitReg(MISCREG_CNTHP_TVAL_EL2).mapsTo(MISCREG_CNTHP_TVAL);
126 InitReg(MISCREG_CNTKCTL_EL1).mapsTo(MISCREG_CNTKCTL);
127 InitReg(MISCREG_CNTP_CTL_EL0).mapsTo(MISCREG_CNTP_CTL_NS);
128 InitReg(MISCREG_CNTP_CVAL_EL0).mapsTo(MISCREG_CNTP_CVAL_NS); /* 64b */
129 InitReg(MISCREG_CNTP_TVAL_EL0).mapsTo(MISCREG_CNTP_TVAL_NS);
130 InitReg(MISCREG_CNTPCT_EL0).mapsTo(MISCREG_CNTPCT); /* 64b */
131 InitReg(MISCREG_CNTV_CTL_EL0).mapsTo(MISCREG_CNTV_CTL);
132 InitReg(MISCREG_CNTV_CVAL_EL0).mapsTo(MISCREG_CNTV_CVAL); /* 64b */
133 InitReg(MISCREG_CNTV_TVAL_EL0).mapsTo(MISCREG_CNTV_TVAL);
134 InitReg(MISCREG_CNTVCT_EL0).mapsTo(MISCREG_CNTVCT); /* 64b */
135 InitReg(MISCREG_CNTVOFF_EL2).mapsTo(MISCREG_CNTVOFF); /* 64b */
136 InitReg(MISCREG_DBGAUTHSTATUS_EL1).mapsTo(MISCREG_DBGAUTHSTATUS);
137 InitReg(MISCREG_DBGBCR0_EL1).mapsTo(MISCREG_DBGBCR0);
138 InitReg(MISCREG_DBGBCR1_EL1).mapsTo(MISCREG_DBGBCR1);
139 InitReg(MISCREG_DBGBCR2_EL1).mapsTo(MISCREG_DBGBCR2);
140 InitReg(MISCREG_DBGBCR3_EL1).mapsTo(MISCREG_DBGBCR3);
141 InitReg(MISCREG_DBGBCR4_EL1).mapsTo(MISCREG_DBGBCR4);
142 InitReg(MISCREG_DBGBCR5_EL1).mapsTo(MISCREG_DBGBCR5);
143 InitReg(MISCREG_DBGBVR0_EL1).mapsTo(MISCREG_DBGBVR0 /*,
144 MISCREG_DBGBXVR0 */);
145 InitReg(MISCREG_DBGBVR1_EL1).mapsTo(MISCREG_DBGBVR1 /*,
146 MISCREG_DBGBXVR1 */);
147 InitReg(MISCREG_DBGBVR2_EL1).mapsTo(MISCREG_DBGBVR2 /*,
148 MISCREG_DBGBXVR2 */);
149 InitReg(MISCREG_DBGBVR3_EL1).mapsTo(MISCREG_DBGBVR3 /*,
150 MISCREG_DBGBXVR3 */);
151 InitReg(MISCREG_DBGBVR4_EL1).mapsTo(MISCREG_DBGBVR4 /*,
152 MISCREG_DBGBXVR4 */);
153 InitReg(MISCREG_DBGBVR5_EL1).mapsTo(MISCREG_DBGBVR5 /*,
154 MISCREG_DBGBXVR5 */);
155 InitReg(MISCREG_DBGCLAIMSET_EL1).mapsTo(MISCREG_DBGCLAIMSET);
156 InitReg(MISCREG_DBGCLAIMCLR_EL1).mapsTo(MISCREG_DBGCLAIMCLR);
157 // DBGDTR_EL0 -> DBGDTR{R or T}Xint
158 // DBGDTRRX_EL0 -> DBGDTRRXint
159 // DBGDTRTX_EL0 -> DBGDTRRXint
160 InitReg(MISCREG_DBGPRCR_EL1).mapsTo(MISCREG_DBGPRCR);
161 InitReg(MISCREG_DBGVCR32_EL2).mapsTo(MISCREG_DBGVCR);
162 InitReg(MISCREG_DBGWCR0_EL1).mapsTo(MISCREG_DBGWCR0);
163 InitReg(MISCREG_DBGWCR1_EL1).mapsTo(MISCREG_DBGWCR1);
164 InitReg(MISCREG_DBGWCR2_EL1).mapsTo(MISCREG_DBGWCR2);
165 InitReg(MISCREG_DBGWCR3_EL1).mapsTo(MISCREG_DBGWCR3);
166 InitReg(MISCREG_DBGWVR0_EL1).mapsTo(MISCREG_DBGWVR0);
167 InitReg(MISCREG_DBGWVR1_EL1).mapsTo(MISCREG_DBGWVR1);
168 InitReg(MISCREG_DBGWVR2_EL1).mapsTo(MISCREG_DBGWVR2);
169 InitReg(MISCREG_DBGWVR3_EL1).mapsTo(MISCREG_DBGWVR3);
170 InitReg(MISCREG_ID_DFR0_EL1).mapsTo(MISCREG_ID_DFR0);
171 InitReg(MISCREG_MDCCSR_EL0).mapsTo(MISCREG_DBGDSCRint);
172 InitReg(MISCREG_MDRAR_EL1).mapsTo(MISCREG_DBGDRAR);
173 InitReg(MISCREG_MDSCR_EL1).mapsTo(MISCREG_DBGDSCRext);
174 InitReg(MISCREG_OSDLR_EL1).mapsTo(MISCREG_DBGOSDLR);
175 InitReg(MISCREG_OSDTRRX_EL1).mapsTo(MISCREG_DBGDTRRXext);
176 InitReg(MISCREG_OSDTRTX_EL1).mapsTo(MISCREG_DBGDTRTXext);
177 InitReg(MISCREG_OSECCR_EL1).mapsTo(MISCREG_DBGOSECCR);
178 InitReg(MISCREG_OSLAR_EL1).mapsTo(MISCREG_DBGOSLAR);
179 InitReg(MISCREG_OSLSR_EL1).mapsTo(MISCREG_DBGOSLSR);
180 InitReg(MISCREG_PMCCNTR_EL0).mapsTo(MISCREG_PMCCNTR);
181 InitReg(MISCREG_PMCEID0_EL0).mapsTo(MISCREG_PMCEID0);
182 InitReg(MISCREG_PMCEID1_EL0).mapsTo(MISCREG_PMCEID1);
183 InitReg(MISCREG_PMCNTENSET_EL0).mapsTo(MISCREG_PMCNTENSET);
184 InitReg(MISCREG_PMCNTENCLR_EL0).mapsTo(MISCREG_PMCNTENCLR);
185 InitReg(MISCREG_PMCR_EL0).mapsTo(MISCREG_PMCR);
186/* InitReg(MISCREG_PMEVCNTR0_EL0).mapsTo(MISCREG_PMEVCNTR0);
187 InitReg(MISCREG_PMEVCNTR1_EL0).mapsTo(MISCREG_PMEVCNTR1);
188 InitReg(MISCREG_PMEVCNTR2_EL0).mapsTo(MISCREG_PMEVCNTR2);
189 InitReg(MISCREG_PMEVCNTR3_EL0).mapsTo(MISCREG_PMEVCNTR3);
190 InitReg(MISCREG_PMEVCNTR4_EL0).mapsTo(MISCREG_PMEVCNTR4);
191 InitReg(MISCREG_PMEVCNTR5_EL0).mapsTo(MISCREG_PMEVCNTR5);
192 InitReg(MISCREG_PMEVTYPER0_EL0).mapsTo(MISCREG_PMEVTYPER0);
193 InitReg(MISCREG_PMEVTYPER1_EL0).mapsTo(MISCREG_PMEVTYPER1);
194 InitReg(MISCREG_PMEVTYPER2_EL0).mapsTo(MISCREG_PMEVTYPER2);
195 InitReg(MISCREG_PMEVTYPER3_EL0).mapsTo(MISCREG_PMEVTYPER3);
196 InitReg(MISCREG_PMEVTYPER4_EL0).mapsTo(MISCREG_PMEVTYPER4);
197 InitReg(MISCREG_PMEVTYPER5_EL0).mapsTo(MISCREG_PMEVTYPER5); */
198 InitReg(MISCREG_PMINTENCLR_EL1).mapsTo(MISCREG_PMINTENCLR);
199 InitReg(MISCREG_PMINTENSET_EL1).mapsTo(MISCREG_PMINTENSET);
200// InitReg(MISCREG_PMOVSCLR_EL0).mapsTo(MISCREG_PMOVSCLR);
201 InitReg(MISCREG_PMOVSSET_EL0).mapsTo(MISCREG_PMOVSSET);
202 InitReg(MISCREG_PMSELR_EL0).mapsTo(MISCREG_PMSELR);
203 InitReg(MISCREG_PMSWINC_EL0).mapsTo(MISCREG_PMSWINC);
204 InitReg(MISCREG_PMUSERENR_EL0).mapsTo(MISCREG_PMUSERENR);
205 InitReg(MISCREG_PMXEVCNTR_EL0).mapsTo(MISCREG_PMXEVCNTR);
206 InitReg(MISCREG_PMXEVTYPER_EL0).mapsTo(MISCREG_PMXEVTYPER);
207
208 InitReg(MISCREG_SCR).res0(0xff40) // [31:16], [6]
209 .res1(0x0030); // [5:4]
210
211 // from ARM DDI 0487A.i, template text
212 // "AArch64 System register ___ can be mapped to
213 // AArch32 System register ___, but this is not
214 // architecturally mandated."
215 InitReg(MISCREG_SCR_EL3).mapsTo(MISCREG_SCR); // D7-2005
216 // MDCR_EL3 -> SDCR, D7-2108 (the latter is unimpl. in gem5)
217 InitReg(MISCREG_SPSR_EL1).mapsTo(MISCREG_SPSR_SVC); // C5.2.17 SPSR_EL1
218 InitReg(MISCREG_SPSR_EL2).mapsTo(MISCREG_SPSR_HYP); // C5.2.18 SPSR_EL2
219 InitReg(MISCREG_SPSR_EL3).mapsTo(MISCREG_SPSR_MON); // C5.2.19 SPSR_EL3
220}
221
222ISA::ISA(Params *p)
223 : SimObject(p),
224 system(NULL),
225 _decoderFlavour(p->decoderFlavour),
226 _vecRegRenameMode(p->vecRegRenameMode),
58ISA::ISA(Params *p)
59 : SimObject(p),
60 system(NULL),
61 _decoderFlavour(p->decoderFlavour),
62 _vecRegRenameMode(p->vecRegRenameMode),
227 pmu(p->pmu),
228 lookUpMiscReg(NUM_MISCREGS)
63 pmu(p->pmu)
229{
230 miscRegs[MISCREG_SCTLR_RST] = 0;
231
232 // Hook up a dummy device if we haven't been configured with a
233 // real PMU. By using a dummy device, we don't need to check that
234 // the PMU exist every time we try to access a PMU register.
235 if (!pmu)
236 pmu = &dummyDevice;

--- 19 unchanged lines hidden (view full) ---

256 }
257
258 initializeMiscRegMetadata();
259 preUnflattenMiscReg();
260
261 clear();
262}
263
64{
65 miscRegs[MISCREG_SCTLR_RST] = 0;
66
67 // Hook up a dummy device if we haven't been configured with a
68 // real PMU. By using a dummy device, we don't need to check that
69 // the PMU exist every time we try to access a PMU register.
70 if (!pmu)
71 pmu = &dummyDevice;

--- 19 unchanged lines hidden (view full) ---

91 }
92
93 initializeMiscRegMetadata();
94 preUnflattenMiscReg();
95
96 clear();
97}
98
99std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS);
100
264const ArmISAParams *
265ISA::params() const
266{
267 return dynamic_cast<const Params *>(_params);
268}
269
270void
271ISA::clear()

--- 1780 unchanged lines hidden --- 		101const ArmISAParams *
102ISA::params() const
103{
104 return dynamic_cast<const Params *>(_params);
105}
106
107void
108ISA::clear()

--- 1780 unchanged lines hidden ---