isa.cc (12392:e0dbdf30a2a5) isa.cc (12406:86bde4a026b5)
1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 25 unchanged lines hidden (view full) ---

34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42
43#include "arch/arm/pmu.hh"
44#include "arch/arm/system.hh"
42#include "arch/arm/pmu.hh"
43#include "arch/arm/system.hh"
44#include "arch/arm/tlb.hh"
45#include "cpu/base.hh"
46#include "cpu/checker/cpu.hh"
47#include "debug/Arm.hh"
48#include "debug/MiscRegs.hh"
49#include "dev/arm/generic_timer.hh"
50#include "params/ArmISA.hh"
51#include "sim/faults.hh"
52#include "sim/stat_control.hh"

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816 misc_reg, lower, upper, val);
817 } else {
818 miscRegs[lower] = val;
819 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n",
820 misc_reg, lower, val);
821 }
822}
823
45#include "cpu/base.hh"
46#include "cpu/checker/cpu.hh"
47#include "debug/Arm.hh"
48#include "debug/MiscRegs.hh"
49#include "dev/arm/generic_timer.hh"
50#include "params/ArmISA.hh"
51#include "sim/faults.hh"
52#include "sim/stat_control.hh"

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816 misc_reg, lower, upper, val);
817 } else {
818 miscRegs[lower] = val;
819 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n",
820 misc_reg, lower, val);
821 }
822}
823
824namespace {
825
826template<typename T>
827TLB *
828getITBPtr(T *tc)
829{
830 auto tlb = dynamic_cast<TLB *>(tc->getITBPtr());
831 assert(tlb);
832 return tlb;
833}
834
835template<typename T>
836TLB *
837getDTBPtr(T *tc)
838{
839 auto tlb = dynamic_cast<TLB *>(tc->getDTBPtr());
840 assert(tlb);
841 return tlb;
842}
843
844} // anonymous namespace
845
824void
825ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
826{
827
828 MiscReg newVal = val;
829 int x;
830 bool secure_lookup;
831 bool hyp;

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838 if (misc_reg == MISCREG_CPSR) {
839 updateRegMap(val);
840
841
842 CPSR old_cpsr = miscRegs[MISCREG_CPSR];
843 int old_mode = old_cpsr.mode;
844 CPSR cpsr = val;
845 if (old_mode != cpsr.mode) {
846void
847ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
848{
849
850 MiscReg newVal = val;
851 int x;
852 bool secure_lookup;
853 bool hyp;

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860 if (misc_reg == MISCREG_CPSR) {
861 updateRegMap(val);
862
863
864 CPSR old_cpsr = miscRegs[MISCREG_CPSR];
865 int old_mode = old_cpsr.mode;
866 CPSR cpsr = val;
867 if (old_mode != cpsr.mode) {
846 tc->getITBPtr()->invalidateMiscReg();
847 tc->getDTBPtr()->invalidateMiscReg();
868 getITBPtr(tc)->invalidateMiscReg();
869 getDTBPtr(tc)->invalidateMiscReg();
848 }
849
850 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
851 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
852 PCState pc = tc->pcState();
853 pc.nextThumb(cpsr.t);
854 pc.nextJazelle(cpsr.j);
855

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1083 // ARM ARM (ARM DDI 0406C.b) B4.1.5
1084 // Valid only with LPAE
1085 if (!haveLPAE)
1086 return;
1087 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal);
1088 }
1089 break;
1090 case MISCREG_SCR:
870 }
871
872 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
873 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
874 PCState pc = tc->pcState();
875 pc.nextThumb(cpsr.t);
876 pc.nextJazelle(cpsr.j);
877

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1105 // ARM ARM (ARM DDI 0406C.b) B4.1.5
1106 // Valid only with LPAE
1107 if (!haveLPAE)
1108 return;
1109 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal);
1110 }
1111 break;
1112 case MISCREG_SCR:
1091 tc->getITBPtr()->invalidateMiscReg();
1092 tc->getDTBPtr()->invalidateMiscReg();
1113 getITBPtr(tc)->invalidateMiscReg();
1114 getDTBPtr(tc)->invalidateMiscReg();
1093 break;
1094 case MISCREG_SCTLR:
1095 {
1096 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
1097 scr = readMiscRegNoEffect(MISCREG_SCR);
1098 MiscRegIndex sctlr_idx = (haveSecurity && !scr.ns)
1099 ? MISCREG_SCTLR_S : MISCREG_SCTLR_NS;
1100 SCTLR sctlr = miscRegs[sctlr_idx];
1101 SCTLR new_sctlr = newVal;
1102 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization;
1103 miscRegs[sctlr_idx] = (MiscReg)new_sctlr;
1115 break;
1116 case MISCREG_SCTLR:
1117 {
1118 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
1119 scr = readMiscRegNoEffect(MISCREG_SCR);
1120 MiscRegIndex sctlr_idx = (haveSecurity && !scr.ns)
1121 ? MISCREG_SCTLR_S : MISCREG_SCTLR_NS;
1122 SCTLR sctlr = miscRegs[sctlr_idx];
1123 SCTLR new_sctlr = newVal;
1124 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization;
1125 miscRegs[sctlr_idx] = (MiscReg)new_sctlr;
1104 tc->getITBPtr()->invalidateMiscReg();
1105 tc->getDTBPtr()->invalidateMiscReg();
1126 getITBPtr(tc)->invalidateMiscReg();
1127 getDTBPtr(tc)->invalidateMiscReg();
1106 }
1107 case MISCREG_MIDR:
1108 case MISCREG_ID_PFR0:
1109 case MISCREG_ID_PFR1:
1110 case MISCREG_ID_DFR0:
1111 case MISCREG_ID_MMFR0:
1112 case MISCREG_ID_MMFR1:
1113 case MISCREG_ID_MMFR2:

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1143 case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
1144 assert32(tc);
1145 target_el = 1; // el 0 and 1 are handled together
1146 scr = readMiscReg(MISCREG_SCR, tc);
1147 secure_lookup = haveSecurity && !scr.ns;
1148 sys = tc->getSystemPtr();
1149 for (x = 0; x < sys->numContexts(); x++) {
1150 oc = sys->getThreadContext(x);
1128 }
1129 case MISCREG_MIDR:
1130 case MISCREG_ID_PFR0:
1131 case MISCREG_ID_PFR1:
1132 case MISCREG_ID_DFR0:
1133 case MISCREG_ID_MMFR0:
1134 case MISCREG_ID_MMFR1:
1135 case MISCREG_ID_MMFR2:

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1165 case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
1166 assert32(tc);
1167 target_el = 1; // el 0 and 1 are handled together
1168 scr = readMiscReg(MISCREG_SCR, tc);
1169 secure_lookup = haveSecurity && !scr.ns;
1170 sys = tc->getSystemPtr();
1171 for (x = 0; x < sys->numContexts(); x++) {
1172 oc = sys->getThreadContext(x);
1151 assert(oc->getITBPtr() && oc->getDTBPtr());
1152 oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el);
1153 oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el);
1173 getITBPtr(oc)->flushAllSecurity(secure_lookup, target_el);
1174 getDTBPtr(oc)->flushAllSecurity(secure_lookup, target_el);
1154
1155 // If CheckerCPU is connected, need to notify it of a flush
1156 CheckerCPU *checker = oc->getCheckerCpuPtr();
1157 if (checker) {
1175
1176 // If CheckerCPU is connected, need to notify it of a flush
1177 CheckerCPU *checker = oc->getCheckerCpuPtr();
1178 if (checker) {
1158 checker->getITBPtr()->flushAllSecurity(secure_lookup,
1159 target_el);
1160 checker->getDTBPtr()->flushAllSecurity(secure_lookup,
1161 target_el);
1179 getITBPtr(checker)->flushAllSecurity(secure_lookup,
1180 target_el);
1181 getDTBPtr(checker)->flushAllSecurity(secure_lookup,
1182 target_el);
1162 }
1163 }
1164 return;
1165 // TLBI all entries, EL0&1, instruction side
1166 case MISCREG_ITLBIALL:
1167 assert32(tc);
1168 target_el = 1; // el 0 and 1 are handled together
1169 scr = readMiscReg(MISCREG_SCR, tc);
1170 secure_lookup = haveSecurity && !scr.ns;
1183 }
1184 }
1185 return;
1186 // TLBI all entries, EL0&1, instruction side
1187 case MISCREG_ITLBIALL:
1188 assert32(tc);
1189 target_el = 1; // el 0 and 1 are handled together
1190 scr = readMiscReg(MISCREG_SCR, tc);
1191 secure_lookup = haveSecurity && !scr.ns;
1171 tc->getITBPtr()->flushAllSecurity(secure_lookup, target_el);
1192 getITBPtr(tc)->flushAllSecurity(secure_lookup, target_el);
1172 return;
1173 // TLBI all entries, EL0&1, data side
1174 case MISCREG_DTLBIALL:
1175 assert32(tc);
1176 target_el = 1; // el 0 and 1 are handled together
1177 scr = readMiscReg(MISCREG_SCR, tc);
1178 secure_lookup = haveSecurity && !scr.ns;
1193 return;
1194 // TLBI all entries, EL0&1, data side
1195 case MISCREG_DTLBIALL:
1196 assert32(tc);
1197 target_el = 1; // el 0 and 1 are handled together
1198 scr = readMiscReg(MISCREG_SCR, tc);
1199 secure_lookup = haveSecurity && !scr.ns;
1179 tc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el);
1200 getDTBPtr(tc)->flushAllSecurity(secure_lookup, target_el);
1180 return;
1181 // TLBI based on VA, EL0&1 inner sharable (ignored)
1182 case MISCREG_TLBIMVAIS:
1183 case MISCREG_TLBIMVA:
1184 assert32(tc);
1185 target_el = 1; // el 0 and 1 are handled together
1186 scr = readMiscReg(MISCREG_SCR, tc);
1187 secure_lookup = haveSecurity && !scr.ns;
1188 sys = tc->getSystemPtr();
1189 for (x = 0; x < sys->numContexts(); x++) {
1190 oc = sys->getThreadContext(x);
1201 return;
1202 // TLBI based on VA, EL0&1 inner sharable (ignored)
1203 case MISCREG_TLBIMVAIS:
1204 case MISCREG_TLBIMVA:
1205 assert32(tc);
1206 target_el = 1; // el 0 and 1 are handled together
1207 scr = readMiscReg(MISCREG_SCR, tc);
1208 secure_lookup = haveSecurity && !scr.ns;
1209 sys = tc->getSystemPtr();
1210 for (x = 0; x < sys->numContexts(); x++) {
1211 oc = sys->getThreadContext(x);
1191 assert(oc->getITBPtr() && oc->getDTBPtr());
1192 oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1212 getITBPtr(oc)->flushMvaAsid(mbits(newVal, 31, 12),
1193 bits(newVal, 7,0),
1194 secure_lookup, target_el);
1213 bits(newVal, 7,0),
1214 secure_lookup, target_el);
1195 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1215 getDTBPtr(oc)->flushMvaAsid(mbits(newVal, 31, 12),
1196 bits(newVal, 7,0),
1197 secure_lookup, target_el);
1198
1199 CheckerCPU *checker = oc->getCheckerCpuPtr();
1200 if (checker) {
1216 bits(newVal, 7,0),
1217 secure_lookup, target_el);
1218
1219 CheckerCPU *checker = oc->getCheckerCpuPtr();
1220 if (checker) {
1201 checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1221 getITBPtr(checker)->flushMvaAsid(mbits(newVal, 31, 12),
1202 bits(newVal, 7,0), secure_lookup, target_el);
1222 bits(newVal, 7,0), secure_lookup, target_el);
1203 checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1223 getDTBPtr(checker)->flushMvaAsid(mbits(newVal, 31, 12),
1204 bits(newVal, 7,0), secure_lookup, target_el);
1205 }
1206 }
1207 return;
1208 // TLBI by ASID, EL0&1, inner sharable
1209 case MISCREG_TLBIASIDIS:
1210 case MISCREG_TLBIASID:
1211 assert32(tc);
1212 target_el = 1; // el 0 and 1 are handled together
1213 scr = readMiscReg(MISCREG_SCR, tc);
1214 secure_lookup = haveSecurity && !scr.ns;
1215 sys = tc->getSystemPtr();
1216 for (x = 0; x < sys->numContexts(); x++) {
1217 oc = sys->getThreadContext(x);
1224 bits(newVal, 7,0), secure_lookup, target_el);
1225 }
1226 }
1227 return;
1228 // TLBI by ASID, EL0&1, inner sharable
1229 case MISCREG_TLBIASIDIS:
1230 case MISCREG_TLBIASID:
1231 assert32(tc);
1232 target_el = 1; // el 0 and 1 are handled together
1233 scr = readMiscReg(MISCREG_SCR, tc);
1234 secure_lookup = haveSecurity && !scr.ns;
1235 sys = tc->getSystemPtr();
1236 for (x = 0; x < sys->numContexts(); x++) {
1237 oc = sys->getThreadContext(x);
1218 assert(oc->getITBPtr() && oc->getDTBPtr());
1219 oc->getITBPtr()->flushAsid(bits(newVal, 7,0),
1238 getITBPtr(oc)->flushAsid(bits(newVal, 7,0),
1220 secure_lookup, target_el);
1239 secure_lookup, target_el);
1221 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0),
1240 getDTBPtr(oc)->flushAsid(bits(newVal, 7,0),
1222 secure_lookup, target_el);
1223 CheckerCPU *checker = oc->getCheckerCpuPtr();
1224 if (checker) {
1241 secure_lookup, target_el);
1242 CheckerCPU *checker = oc->getCheckerCpuPtr();
1243 if (checker) {
1225 checker->getITBPtr()->flushAsid(bits(newVal, 7,0),
1244 getITBPtr(checker)->flushAsid(bits(newVal, 7,0),
1226 secure_lookup, target_el);
1245 secure_lookup, target_el);
1227 checker->getDTBPtr()->flushAsid(bits(newVal, 7,0),
1246 getDTBPtr(checker)->flushAsid(bits(newVal, 7,0),
1228 secure_lookup, target_el);
1229 }
1230 }
1231 return;
1232 // TLBI by address, EL0&1, inner sharable (ignored)
1233 case MISCREG_TLBIMVAAIS:
1234 case MISCREG_TLBIMVAA:
1235 assert32(tc);

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1250 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el);
1251 return;
1252 // TLBI by address and asid, EL0&1, instruction side only
1253 case MISCREG_ITLBIMVA:
1254 assert32(tc);
1255 target_el = 1; // el 0 and 1 are handled together
1256 scr = readMiscReg(MISCREG_SCR, tc);
1257 secure_lookup = haveSecurity && !scr.ns;
1247 secure_lookup, target_el);
1248 }
1249 }
1250 return;
1251 // TLBI by address, EL0&1, inner sharable (ignored)
1252 case MISCREG_TLBIMVAAIS:
1253 case MISCREG_TLBIMVAA:
1254 assert32(tc);

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1269 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el);
1270 return;
1271 // TLBI by address and asid, EL0&1, instruction side only
1272 case MISCREG_ITLBIMVA:
1273 assert32(tc);
1274 target_el = 1; // el 0 and 1 are handled together
1275 scr = readMiscReg(MISCREG_SCR, tc);
1276 secure_lookup = haveSecurity && !scr.ns;
1258 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1277 getITBPtr(tc)->flushMvaAsid(mbits(newVal, 31, 12),
1259 bits(newVal, 7,0), secure_lookup, target_el);
1260 return;
1261 // TLBI by address and asid, EL0&1, data side only
1262 case MISCREG_DTLBIMVA:
1263 assert32(tc);
1264 target_el = 1; // el 0 and 1 are handled together
1265 scr = readMiscReg(MISCREG_SCR, tc);
1266 secure_lookup = haveSecurity && !scr.ns;
1278 bits(newVal, 7,0), secure_lookup, target_el);
1279 return;
1280 // TLBI by address and asid, EL0&1, data side only
1281 case MISCREG_DTLBIMVA:
1282 assert32(tc);
1283 target_el = 1; // el 0 and 1 are handled together
1284 scr = readMiscReg(MISCREG_SCR, tc);
1285 secure_lookup = haveSecurity && !scr.ns;
1267 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
1286 getDTBPtr(tc)->flushMvaAsid(mbits(newVal, 31, 12),
1268 bits(newVal, 7,0), secure_lookup, target_el);
1269 return;
1270 // TLBI by ASID, EL0&1, instrution side only
1271 case MISCREG_ITLBIASID:
1272 assert32(tc);
1273 target_el = 1; // el 0 and 1 are handled together
1274 scr = readMiscReg(MISCREG_SCR, tc);
1275 secure_lookup = haveSecurity && !scr.ns;
1287 bits(newVal, 7,0), secure_lookup, target_el);
1288 return;
1289 // TLBI by ASID, EL0&1, instrution side only
1290 case MISCREG_ITLBIASID:
1291 assert32(tc);
1292 target_el = 1; // el 0 and 1 are handled together
1293 scr = readMiscReg(MISCREG_SCR, tc);
1294 secure_lookup = haveSecurity && !scr.ns;
1276 tc->getITBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup,
1295 getITBPtr(tc)->flushAsid(bits(newVal, 7,0), secure_lookup,
1277 target_el);
1278 return;
1279 // TLBI by ASID EL0&1 data size only
1280 case MISCREG_DTLBIASID:
1281 assert32(tc);
1282 target_el = 1; // el 0 and 1 are handled together
1283 scr = readMiscReg(MISCREG_SCR, tc);
1284 secure_lookup = haveSecurity && !scr.ns;
1296 target_el);
1297 return;
1298 // TLBI by ASID EL0&1 data size only
1299 case MISCREG_DTLBIASID:
1300 assert32(tc);
1301 target_el = 1; // el 0 and 1 are handled together
1302 scr = readMiscReg(MISCREG_SCR, tc);
1303 secure_lookup = haveSecurity && !scr.ns;
1285 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup,
1304 getDTBPtr(tc)->flushAsid(bits(newVal, 7,0), secure_lookup,
1286 target_el);
1287 return;
1288 // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB
1289 case MISCREG_TLBIALLNSNH:
1290 case MISCREG_TLBIALLNSNHIS:
1291 assert32(tc);
1292 target_el = 1; // el 0 and 1 are handled together
1293 hyp = 0;

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1375 case MISCREG_TLBI_ASIDE1_Xt:
1376 assert64(tc);
1377 target_el = 1; // el 0 and 1 are handled together
1378 scr = readMiscReg(MISCREG_SCR, tc);
1379 secure_lookup = haveSecurity && !scr.ns;
1380 sys = tc->getSystemPtr();
1381 for (x = 0; x < sys->numContexts(); x++) {
1382 oc = sys->getThreadContext(x);
1305 target_el);
1306 return;
1307 // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB
1308 case MISCREG_TLBIALLNSNH:
1309 case MISCREG_TLBIALLNSNHIS:
1310 assert32(tc);
1311 target_el = 1; // el 0 and 1 are handled together
1312 hyp = 0;

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1394 case MISCREG_TLBI_ASIDE1_Xt:
1395 assert64(tc);
1396 target_el = 1; // el 0 and 1 are handled together
1397 scr = readMiscReg(MISCREG_SCR, tc);
1398 secure_lookup = haveSecurity && !scr.ns;
1399 sys = tc->getSystemPtr();
1400 for (x = 0; x < sys->numContexts(); x++) {
1401 oc = sys->getThreadContext(x);
1383 assert(oc->getITBPtr() && oc->getDTBPtr());
1384 asid = bits(newVal, 63, 48);
1385 if (!haveLargeAsid64)
1386 asid &= mask(8);
1402 asid = bits(newVal, 63, 48);
1403 if (!haveLargeAsid64)
1404 asid &= mask(8);
1387 oc->getITBPtr()->flushAsid(asid, secure_lookup, target_el);
1388 oc->getDTBPtr()->flushAsid(asid, secure_lookup, target_el);
1405 getITBPtr(oc)->flushAsid(asid, secure_lookup, target_el);
1406 getDTBPtr(oc)->flushAsid(asid, secure_lookup, target_el);
1389 CheckerCPU *checker = oc->getCheckerCpuPtr();
1390 if (checker) {
1407 CheckerCPU *checker = oc->getCheckerCpuPtr();
1408 if (checker) {
1391 checker->getITBPtr()->flushAsid(asid,
1409 getITBPtr(checker)->flushAsid(asid,
1392 secure_lookup, target_el);
1410 secure_lookup, target_el);
1393 checker->getDTBPtr()->flushAsid(asid,
1411 getDTBPtr(checker)->flushAsid(asid,
1394 secure_lookup, target_el);
1395 }
1396 }
1397 return;
1398 // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID
1399 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1400 // entries from the last level of translation table walks
1401 // @todo: handle VMID to enable Virtualization

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1406 assert64(tc);
1407 target_el = 1; // el 0 and 1 are handled together
1408 scr = readMiscReg(MISCREG_SCR, tc);
1409 secure_lookup = haveSecurity && !scr.ns;
1410 sys = tc->getSystemPtr();
1411 for (x = 0; x < sys->numContexts(); x++) {
1412 // @todo: extra controls on TLBI broadcast?
1413 oc = sys->getThreadContext(x);
1412 secure_lookup, target_el);
1413 }
1414 }
1415 return;
1416 // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID
1417 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1418 // entries from the last level of translation table walks
1419 // @todo: handle VMID to enable Virtualization

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1424 assert64(tc);
1425 target_el = 1; // el 0 and 1 are handled together
1426 scr = readMiscReg(MISCREG_SCR, tc);
1427 secure_lookup = haveSecurity && !scr.ns;
1428 sys = tc->getSystemPtr();
1429 for (x = 0; x < sys->numContexts(); x++) {
1430 // @todo: extra controls on TLBI broadcast?
1431 oc = sys->getThreadContext(x);
1414 assert(oc->getITBPtr() && oc->getDTBPtr());
1415 Addr va = ((Addr) bits(newVal, 43, 0)) << 12;
1432 Addr va = ((Addr) bits(newVal, 43, 0)) << 12;
1416 oc->getITBPtr()->flushMva(va,
1433 getITBPtr(oc)->flushMva(va,
1417 secure_lookup, false, target_el);
1434 secure_lookup, false, target_el);
1418 oc->getDTBPtr()->flushMva(va,
1435 getDTBPtr(oc)->flushMva(va,
1419 secure_lookup, false, target_el);
1420
1421 CheckerCPU *checker = oc->getCheckerCpuPtr();
1422 if (checker) {
1436 secure_lookup, false, target_el);
1437
1438 CheckerCPU *checker = oc->getCheckerCpuPtr();
1439 if (checker) {
1423 checker->getITBPtr()->flushMva(va,
1440 getITBPtr(checker)->flushMva(va,
1424 secure_lookup, false, target_el);
1441 secure_lookup, false, target_el);
1425 checker->getDTBPtr()->flushMva(va,
1442 getDTBPtr(checker)->flushMva(va,
1426 secure_lookup, false, target_el);
1427 }
1428 }
1429 return;
1430 // AArch64 TLBI: invalidate by IPA, stage 2, current VMID
1431 case MISCREG_TLBI_IPAS2LE1IS_Xt:
1432 case MISCREG_TLBI_IPAS2LE1_Xt:
1433 case MISCREG_TLBI_IPAS2E1IS_Xt:
1434 case MISCREG_TLBI_IPAS2E1_Xt:
1435 assert64(tc);
1436 target_el = 1; // EL 0 and 1 are handled together
1437 scr = readMiscReg(MISCREG_SCR, tc);
1438 secure_lookup = haveSecurity && !scr.ns;
1439 sys = tc->getSystemPtr();
1440 for (x = 0; x < sys->numContexts(); x++) {
1441 oc = sys->getThreadContext(x);
1443 secure_lookup, false, target_el);
1444 }
1445 }
1446 return;
1447 // AArch64 TLBI: invalidate by IPA, stage 2, current VMID
1448 case MISCREG_TLBI_IPAS2LE1IS_Xt:
1449 case MISCREG_TLBI_IPAS2LE1_Xt:
1450 case MISCREG_TLBI_IPAS2E1IS_Xt:
1451 case MISCREG_TLBI_IPAS2E1_Xt:
1452 assert64(tc);
1453 target_el = 1; // EL 0 and 1 are handled together
1454 scr = readMiscReg(MISCREG_SCR, tc);
1455 secure_lookup = haveSecurity && !scr.ns;
1456 sys = tc->getSystemPtr();
1457 for (x = 0; x < sys->numContexts(); x++) {
1458 oc = sys->getThreadContext(x);
1442 assert(oc->getITBPtr() && oc->getDTBPtr());
1443 Addr ipa = ((Addr) bits(newVal, 35, 0)) << 12;
1459 Addr ipa = ((Addr) bits(newVal, 35, 0)) << 12;
1444 oc->getITBPtr()->flushIpaVmid(ipa,
1460 getITBPtr(oc)->flushIpaVmid(ipa,
1445 secure_lookup, false, target_el);
1461 secure_lookup, false, target_el);
1446 oc->getDTBPtr()->flushIpaVmid(ipa,
1462 getDTBPtr(oc)->flushIpaVmid(ipa,
1447 secure_lookup, false, target_el);
1448
1449 CheckerCPU *checker = oc->getCheckerCpuPtr();
1450 if (checker) {
1463 secure_lookup, false, target_el);
1464
1465 CheckerCPU *checker = oc->getCheckerCpuPtr();
1466 if (checker) {
1451 checker->getITBPtr()->flushIpaVmid(ipa,
1467 getITBPtr(checker)->flushIpaVmid(ipa,
1452 secure_lookup, false, target_el);
1468 secure_lookup, false, target_el);
1453 checker->getDTBPtr()->flushIpaVmid(ipa,
1469 getDTBPtr(checker)->flushIpaVmid(ipa,
1454 secure_lookup, false, target_el);
1455 }
1456 }
1457 return;
1458 case MISCREG_ACTLR:
1459 warn("Not doing anything for write of miscreg ACTLR\n");
1460 break;
1461

--- 111 unchanged lines hidden (view full) ---

1573 // functional mode then we're slightly distorting performance
1574 // results obtained from simulations. The translation should be
1575 // done in the same mode the core is running in. NOTE: This
1576 // can't be an atomic translation because that causes problems
1577 // with unexpected atomic snoop requests.
1578 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
1579 Request req(0, val, 0, flags, Request::funcMasterId,
1580 tc->pcState().pc(), tc->contextId());
1470 secure_lookup, false, target_el);
1471 }
1472 }
1473 return;
1474 case MISCREG_ACTLR:
1475 warn("Not doing anything for write of miscreg ACTLR\n");
1476 break;
1477

--- 111 unchanged lines hidden (view full) ---

1589 // functional mode then we're slightly distorting performance
1590 // results obtained from simulations. The translation should be
1591 // done in the same mode the core is running in. NOTE: This
1592 // can't be an atomic translation because that causes problems
1593 // with unexpected atomic snoop requests.
1594 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
1595 Request req(0, val, 0, flags, Request::funcMasterId,
1596 tc->pcState().pc(), tc->contextId());
1581 fault = tc->getDTBPtr()->translateFunctional(&req, tc, mode, tranType);
1597 fault = getDTBPtr(tc)->translateFunctional(
1598 &req, tc, mode, tranType);
1582 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1583 HCR hcr = readMiscRegNoEffect(MISCREG_HCR);
1584
1585 MiscReg newVal;
1586 if (fault == NoFault) {
1587 Addr paddr = req.getPaddr();
1588 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode ||
1589 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) {
1590 newVal = (paddr & mask(39, 12)) |
1599 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1600 HCR hcr = readMiscRegNoEffect(MISCREG_HCR);
1601
1602 MiscReg newVal;
1603 if (fault == NoFault) {
1604 Addr paddr = req.getPaddr();
1605 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode ||
1606 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) {
1607 newVal = (paddr & mask(39, 12)) |
1591 (tc->getDTBPtr()->getAttr());
1608 (getDTBPtr(tc)->getAttr());
1592 } else {
1593 newVal = (paddr & 0xfffff000) |
1609 } else {
1610 newVal = (paddr & 0xfffff000) |
1594 (tc->getDTBPtr()->getAttr());
1611 (getDTBPtr(tc)->getAttr());
1595 }
1596 DPRINTF(MiscRegs,
1597 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
1598 val, newVal);
1599 } else {
1600 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get());
1601 // Set fault bit and FSR
1602 FSR fsr = armFault->getFsr(tc);

--- 62 unchanged lines hidden (view full) ---

1665 uint64_t ttbrMask = mask(63,56) | mask(47,40);
1666 newVal = (newVal & (~ttbrMask));
1667 }
1668 }
1669 }
1670 M5_FALLTHROUGH;
1671 case MISCREG_SCTLR_EL1:
1672 {
1612 }
1613 DPRINTF(MiscRegs,
1614 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
1615 val, newVal);
1616 } else {
1617 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get());
1618 // Set fault bit and FSR
1619 FSR fsr = armFault->getFsr(tc);

--- 62 unchanged lines hidden (view full) ---

1682 uint64_t ttbrMask = mask(63,56) | mask(47,40);
1683 newVal = (newVal & (~ttbrMask));
1684 }
1685 }
1686 }
1687 M5_FALLTHROUGH;
1688 case MISCREG_SCTLR_EL1:
1689 {
1673 tc->getITBPtr()->invalidateMiscReg();
1674 tc->getDTBPtr()->invalidateMiscReg();
1690 getITBPtr(tc)->invalidateMiscReg();
1691 getDTBPtr(tc)->invalidateMiscReg();
1675 setMiscRegNoEffect(misc_reg, newVal);
1676 }
1677 M5_FALLTHROUGH;
1678 case MISCREG_CONTEXTIDR:
1679 case MISCREG_PRRR:
1680 case MISCREG_NMRR:
1681 case MISCREG_MAIR0:
1682 case MISCREG_MAIR1:

--- 6 unchanged lines hidden (view full) ---

1689 case MISCREG_TCR_EL3:
1690 case MISCREG_SCTLR_EL2:
1691 case MISCREG_SCTLR_EL3:
1692 case MISCREG_HSCTLR:
1693 case MISCREG_TTBR0_EL1:
1694 case MISCREG_TTBR1_EL1:
1695 case MISCREG_TTBR0_EL2:
1696 case MISCREG_TTBR0_EL3:
1692 setMiscRegNoEffect(misc_reg, newVal);
1693 }
1694 M5_FALLTHROUGH;
1695 case MISCREG_CONTEXTIDR:
1696 case MISCREG_PRRR:
1697 case MISCREG_NMRR:
1698 case MISCREG_MAIR0:
1699 case MISCREG_MAIR1:

--- 6 unchanged lines hidden (view full) ---

1706 case MISCREG_TCR_EL3:
1707 case MISCREG_SCTLR_EL2:
1708 case MISCREG_SCTLR_EL3:
1709 case MISCREG_HSCTLR:
1710 case MISCREG_TTBR0_EL1:
1711 case MISCREG_TTBR1_EL1:
1712 case MISCREG_TTBR0_EL2:
1713 case MISCREG_TTBR0_EL3:
1697 tc->getITBPtr()->invalidateMiscReg();
1698 tc->getDTBPtr()->invalidateMiscReg();
1714 getITBPtr(tc)->invalidateMiscReg();
1715 getDTBPtr(tc)->invalidateMiscReg();
1699 break;
1700 case MISCREG_NZCV:
1701 {
1702 CPSR cpsr = val;
1703
1704 tc->setCCReg(CCREG_NZ, cpsr.nz);
1705 tc->setCCReg(CCREG_C, cpsr.c);
1706 tc->setCCReg(CCREG_V, cpsr.v);

--- 117 unchanged lines hidden (view full) ---

1824 // results obtained from simulations. The translation should be
1825 // done in the same mode the core is running in. NOTE: This
1826 // can't be an atomic translation because that causes problems
1827 // with unexpected atomic snoop requests.
1828 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
1829 req->setVirt(0, val, 0, flags, Request::funcMasterId,
1830 tc->pcState().pc());
1831 req->setContext(tc->contextId());
1716 break;
1717 case MISCREG_NZCV:
1718 {
1719 CPSR cpsr = val;
1720
1721 tc->setCCReg(CCREG_NZ, cpsr.nz);
1722 tc->setCCReg(CCREG_C, cpsr.c);
1723 tc->setCCReg(CCREG_V, cpsr.v);

--- 117 unchanged lines hidden (view full) ---

1841 // results obtained from simulations. The translation should be
1842 // done in the same mode the core is running in. NOTE: This
1843 // can't be an atomic translation because that causes problems
1844 // with unexpected atomic snoop requests.
1845 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
1846 req->setVirt(0, val, 0, flags, Request::funcMasterId,
1847 tc->pcState().pc());
1848 req->setContext(tc->contextId());
1832 fault = tc->getDTBPtr()->translateFunctional(req, tc, mode,
1833 tranType);
1849 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode,
1850 tranType);
1834
1835 MiscReg newVal;
1836 if (fault == NoFault) {
1837 Addr paddr = req->getPaddr();
1851
1852 MiscReg newVal;
1853 if (fault == NoFault) {
1854 Addr paddr = req->getPaddr();
1838 uint64_t attr = tc->getDTBPtr()->getAttr();
1855 uint64_t attr = getDTBPtr(tc)->getAttr();
1839 uint64_t attr1 = attr >> 56;
1840 if (!attr1 || attr1 ==0x44) {
1841 attr |= 0x100;
1842 attr &= ~ uint64_t(0x80);
1843 }
1844 newVal = (paddr & mask(47, 12)) | attr;
1845 DPRINTF(MiscRegs,
1846 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",

--- 55 unchanged lines hidden (view full) ---

1902 bool secure_lookup, uint8_t target_el)
1903{
1904 if (!haveLargeAsid64)
1905 asid &= mask(8);
1906 Addr va = ((Addr) bits(newVal, 43, 0)) << 12;
1907 System *sys = tc->getSystemPtr();
1908 for (int x = 0; x < sys->numContexts(); x++) {
1909 ThreadContext *oc = sys->getThreadContext(x);
1856 uint64_t attr1 = attr >> 56;
1857 if (!attr1 || attr1 ==0x44) {
1858 attr |= 0x100;
1859 attr &= ~ uint64_t(0x80);
1860 }
1861 newVal = (paddr & mask(47, 12)) | attr;
1862 DPRINTF(MiscRegs,
1863 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",

--- 55 unchanged lines hidden (view full) ---

1919 bool secure_lookup, uint8_t target_el)
1920{
1921 if (!haveLargeAsid64)
1922 asid &= mask(8);
1923 Addr va = ((Addr) bits(newVal, 43, 0)) << 12;
1924 System *sys = tc->getSystemPtr();
1925 for (int x = 0; x < sys->numContexts(); x++) {
1926 ThreadContext *oc = sys->getThreadContext(x);
1910 assert(oc->getITBPtr() && oc->getDTBPtr());
1911 oc->getITBPtr()->flushMvaAsid(va, asid,
1927 getITBPtr(oc)->flushMvaAsid(va, asid,
1912 secure_lookup, target_el);
1928 secure_lookup, target_el);
1913 oc->getDTBPtr()->flushMvaAsid(va, asid,
1929 getDTBPtr(oc)->flushMvaAsid(va, asid,
1914 secure_lookup, target_el);
1915
1916 CheckerCPU *checker = oc->getCheckerCpuPtr();
1917 if (checker) {
1930 secure_lookup, target_el);
1931
1932 CheckerCPU *checker = oc->getCheckerCpuPtr();
1933 if (checker) {
1918 checker->getITBPtr()->flushMvaAsid(
1934 getITBPtr(checker)->flushMvaAsid(
1919 va, asid, secure_lookup, target_el);
1935 va, asid, secure_lookup, target_el);
1920 checker->getDTBPtr()->flushMvaAsid(
1936 getDTBPtr(checker)->flushMvaAsid(
1921 va, asid, secure_lookup, target_el);
1922 }
1923 }
1924}
1925
1926void
1927ISA::tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el)
1928{
1929 System *sys = tc->getSystemPtr();
1930 for (int x = 0; x < sys->numContexts(); x++) {
1931 ThreadContext *oc = sys->getThreadContext(x);
1937 va, asid, secure_lookup, target_el);
1938 }
1939 }
1940}
1941
1942void
1943ISA::tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el)
1944{
1945 System *sys = tc->getSystemPtr();
1946 for (int x = 0; x < sys->numContexts(); x++) {
1947 ThreadContext *oc = sys->getThreadContext(x);
1932 assert(oc->getITBPtr() && oc->getDTBPtr());
1933 oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el);
1934 oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el);
1948 getITBPtr(oc)->flushAllSecurity(secure_lookup, target_el);
1949 getDTBPtr(oc)->flushAllSecurity(secure_lookup, target_el);
1935
1936 // If CheckerCPU is connected, need to notify it of a flush
1937 CheckerCPU *checker = oc->getCheckerCpuPtr();
1938 if (checker) {
1950
1951 // If CheckerCPU is connected, need to notify it of a flush
1952 CheckerCPU *checker = oc->getCheckerCpuPtr();
1953 if (checker) {
1939 checker->getITBPtr()->flushAllSecurity(secure_lookup,
1954 getITBPtr(checker)->flushAllSecurity(secure_lookup,
1940 target_el);
1955 target_el);
1941 checker->getDTBPtr()->flushAllSecurity(secure_lookup,
1956 getDTBPtr(checker)->flushAllSecurity(secure_lookup,
1942 target_el);
1943 }
1944 }
1945}
1946
1947void
1948ISA::tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el)
1949{
1950 System *sys = tc->getSystemPtr();
1951 for (int x = 0; x < sys->numContexts(); x++) {
1952 ThreadContext *oc = sys->getThreadContext(x);
1957 target_el);
1958 }
1959 }
1960}
1961
1962void
1963ISA::tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el)
1964{
1965 System *sys = tc->getSystemPtr();
1966 for (int x = 0; x < sys->numContexts(); x++) {
1967 ThreadContext *oc = sys->getThreadContext(x);
1953 assert(oc->getITBPtr() && oc->getDTBPtr());
1954 oc->getITBPtr()->flushAllNs(hyp, target_el);
1955 oc->getDTBPtr()->flushAllNs(hyp, target_el);
1968 getITBPtr(oc)->flushAllNs(hyp, target_el);
1969 getDTBPtr(oc)->flushAllNs(hyp, target_el);
1956
1957 CheckerCPU *checker = oc->getCheckerCpuPtr();
1958 if (checker) {
1970
1971 CheckerCPU *checker = oc->getCheckerCpuPtr();
1972 if (checker) {
1959 checker->getITBPtr()->flushAllNs(hyp, target_el);
1960 checker->getDTBPtr()->flushAllNs(hyp, target_el);
1973 getITBPtr(checker)->flushAllNs(hyp, target_el);
1974 getDTBPtr(checker)->flushAllNs(hyp, target_el);
1961 }
1962 }
1963}
1964
1965void
1966ISA::tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp,
1967 uint8_t target_el)
1968{
1969 System *sys = tc->getSystemPtr();
1970 for (int x = 0; x < sys->numContexts(); x++) {
1971 ThreadContext *oc = sys->getThreadContext(x);
1975 }
1976 }
1977}
1978
1979void
1980ISA::tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp,
1981 uint8_t target_el)
1982{
1983 System *sys = tc->getSystemPtr();
1984 for (int x = 0; x < sys->numContexts(); x++) {
1985 ThreadContext *oc = sys->getThreadContext(x);
1972 assert(oc->getITBPtr() && oc->getDTBPtr());
1973 oc->getITBPtr()->flushMva(mbits(newVal, 31,12),
1986 getITBPtr(oc)->flushMva(mbits(newVal, 31,12),
1974 secure_lookup, hyp, target_el);
1987 secure_lookup, hyp, target_el);
1975 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12),
1988 getDTBPtr(oc)->flushMva(mbits(newVal, 31,12),
1976 secure_lookup, hyp, target_el);
1977
1978 CheckerCPU *checker = oc->getCheckerCpuPtr();
1979 if (checker) {
1989 secure_lookup, hyp, target_el);
1990
1991 CheckerCPU *checker = oc->getCheckerCpuPtr();
1992 if (checker) {
1980 checker->getITBPtr()->flushMva(mbits(newVal, 31,12),
1993 getITBPtr(checker)->flushMva(mbits(newVal, 31,12),
1981 secure_lookup, hyp, target_el);
1994 secure_lookup, hyp, target_el);
1982 checker->getDTBPtr()->flushMva(mbits(newVal, 31,12),
1995 getDTBPtr(checker)->flushMva(mbits(newVal, 31,12),
1983 secure_lookup, hyp, target_el);
1984 }
1985 }
1986}
1987
1988BaseISADevice &
1989ISA::getGenericTimer(ThreadContext *tc)
1990{

--- 23 unchanged lines hidden --- 		1996 secure_lookup, hyp, target_el);
1997 }
1998 }
1999}
2000
2001BaseISADevice &
2002ISA::getGenericTimer(ThreadContext *tc)
2003{

--- 23 unchanged lines hidden ---