| isa.cc (11772:baccae81e57e) | isa.cc (11773:9db50b9eacf5) |
|---|---|
| 1/* 2 * Copyright (c) 2010-2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 438 unchanged lines hidden (view full) --- 447 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 448 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 449 450 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 451 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 452 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 453 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 454 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; | 1/* 2 * Copyright (c) 2010-2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 438 unchanged lines hidden (view full) --- 447 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 448 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 449 450 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 451 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 452 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 453 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 454 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; |
| 455 miscRegs[MISCREG_ID_AA64PFR0_EL1] = p->id_aa64pfr0_el1; 456 miscRegs[MISCREG_ID_AA64PFR1_EL1] = p->id_aa64pfr1_el1; | |
| 457 458 miscRegs[MISCREG_ID_DFR0_EL1] = 459 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 460 461 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 462 463 // Enforce consistency with system-level settings... 464 --- 306 unchanged lines hidden (view full) --- 771 case MISCREG_ID_PFR0: 772 // !ThumbEE | !Jazelle | Thumb | ARM 773 return 0x00000031; 774 case MISCREG_ID_PFR1: 775 // !Timer | Virti | !M Profile | TrustZone | ARMv4 776 return 0x00000001 777 | (haveSecurity ? 0x00000010 : 0x0) 778 | (haveVirtualization ? 0x00001000 : 0x0); | 455 456 miscRegs[MISCREG_ID_DFR0_EL1] = 457 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 458 459 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 460 461 // Enforce consistency with system-level settings... 462 --- 306 unchanged lines hidden (view full) --- 769 case MISCREG_ID_PFR0: 770 // !ThumbEE | !Jazelle | Thumb | ARM 771 return 0x00000031; 772 case MISCREG_ID_PFR1: 773 // !Timer | Virti | !M Profile | TrustZone | ARMv4 774 return 0x00000001 775 | (haveSecurity ? 0x00000010 : 0x0) 776 | (haveVirtualization ? 0x00001000 : 0x0); |
| 777 case MISCREG_ID_AA64PFR0_EL1: 778 return 0x0000000000000002 // AArch{64,32} supported at EL0 779 | 0x0000000000000020 // EL1 780 | (haveVirtualization ? 0x0000000000000200 : 0) // EL2 781 | (haveSecurity ? 0x0000000000002000 : 0); // EL3 782 case MISCREG_ID_AA64PFR1_EL1: 783 return 0; // bits [63:0] RES0 (reserved for future use) |
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| 779 780 // Generic Timer registers 781 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 782 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 783 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 784 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 785 return getGenericTimer(tc).readMiscReg(misc_reg); 786 --- 1213 unchanged lines hidden --- | 784 785 // Generic Timer registers 786 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 787 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 788 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 789 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 790 return getGenericTimer(tc).readMiscReg(misc_reg); 791 --- 1213 unchanged lines hidden --- |