isa.cc (11770:0d7119bed18e) isa.cc (11771:764eae95bbbb)
1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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221
222 // Give all ISA devices a pointer to this ISA
223 pmu->setISA(this);
224
225 system = dynamic_cast<ArmSystem *>(p->system);
226
227 // Cache system-level properties
228 if (FullSystem && system) {
1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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221
222 // Give all ISA devices a pointer to this ISA
223 pmu->setISA(this);
224
225 system = dynamic_cast<ArmSystem *>(p->system);
226
227 // Cache system-level properties
228 if (FullSystem && system) {
229 highestELIs64 = system->highestELIs64();
229 haveSecurity = system->haveSecurity();
230 haveLPAE = system->haveLPAE();
231 haveVirtualization = system->haveVirtualization();
232 haveLargeAsid64 = system->haveLargeAsid64();
233 physAddrRange64 = system->physAddrRange64();
234 } else {
230 haveSecurity = system->haveSecurity();
231 haveLPAE = system->haveLPAE();
232 haveVirtualization = system->haveVirtualization();
233 haveLargeAsid64 = system->haveLargeAsid64();
234 physAddrRange64 = system->physAddrRange64();
235 } else {
236 highestELIs64 = true; // ArmSystem::highestELIs64 does the same
235 haveSecurity = haveLPAE = haveVirtualization = false;
236 haveLargeAsid64 = false;
237 physAddrRange64 = 32; // dummy value
238 }
239
240 /** Fill in the miscReg translation table */
241 for (auto sw : MiscRegSwitch) {
242 lookUpMiscReg[sw.index] = sw.entry;

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482 encodePhysAddrRange64(physAddrRange64));
483}
484
485MiscReg
486ISA::readMiscRegNoEffect(int misc_reg) const
487{
488 assert(misc_reg < NumMiscRegs);
489
237 haveSecurity = haveLPAE = haveVirtualization = false;
238 haveLargeAsid64 = false;
239 physAddrRange64 = 32; // dummy value
240 }
241
242 /** Fill in the miscReg translation table */
243 for (auto sw : MiscRegSwitch) {
244 lookUpMiscReg[sw.index] = sw.entry;

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484 encodePhysAddrRange64(physAddrRange64));
485}
486
487MiscReg
488ISA::readMiscRegNoEffect(int misc_reg) const
489{
490 assert(misc_reg < NumMiscRegs);
491
490 int flat_idx = flattenMiscIndex(misc_reg); // Note: indexes of AArch64
491 // registers are left unchanged
492 MiscReg val;
493
494 if (lookUpMiscReg[flat_idx].lower == 0 || flat_idx == MISCREG_SPSR) {
495 if (flat_idx == MISCREG_SPSR)
496 flat_idx = flattenMiscIndex(MISCREG_SPSR);
497 val = miscRegs[flat_idx];
498 } else
499 if (lookUpMiscReg[flat_idx].upper > 0)
500 val = ((miscRegs[lookUpMiscReg[flat_idx].lower] & mask(32))
501 | (miscRegs[lookUpMiscReg[flat_idx].upper] << 32));
502 else
503 val = miscRegs[lookUpMiscReg[flat_idx].lower];
504
505 return val;
492 auto regs = getMiscIndices(misc_reg);
493 int lower = regs.first, upper = regs.second;
494 return !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32))
495 |(miscRegs[upper] << 32));
506}
507
508
509MiscReg
510ISA::readMiscReg(int misc_reg, ThreadContext *tc)
511{
512 CPSR cpsr = 0;
513 PCState pc = 0;

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796 return readMiscRegNoEffect(misc_reg);
797}
798
799void
800ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
801{
802 assert(misc_reg < NumMiscRegs);
803
496}
497
498
499MiscReg
500ISA::readMiscReg(int misc_reg, ThreadContext *tc)
501{
502 CPSR cpsr = 0;
503 PCState pc = 0;

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786 return readMiscRegNoEffect(misc_reg);
787}
788
789void
790ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
791{
792 assert(misc_reg < NumMiscRegs);
793
804 int flat_idx = flattenMiscIndex(misc_reg); // Note: indexes of AArch64
805 // registers are left unchanged
806
807 int flat_idx2 = lookUpMiscReg[flat_idx].upper;
808
809 if (flat_idx2 > 0) {
810 miscRegs[lookUpMiscReg[flat_idx].lower] = bits(val, 31, 0);
811 miscRegs[flat_idx2] = bits(val, 63, 32);
794 auto regs = getMiscIndices(misc_reg);
795 int lower = regs.first, upper = regs.second;
796 if (upper > 0) {
797 miscRegs[lower] = bits(val, 31, 0);
798 miscRegs[upper] = bits(val, 63, 32);
812 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n",
799 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n",
813 misc_reg, flat_idx, flat_idx2, val);
800 misc_reg, lower, upper, val);
814 } else {
801 } else {
815 if (flat_idx == MISCREG_SPSR)
816 flat_idx = flattenMiscIndex(MISCREG_SPSR);
817 else
818 flat_idx = (lookUpMiscReg[flat_idx].lower > 0) ?
819 lookUpMiscReg[flat_idx].lower : flat_idx;
820 miscRegs[flat_idx] = val;
802 miscRegs[lower] = val;
821 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n",
803 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n",
822 misc_reg, flat_idx, val);
804 misc_reg, lower, val);
823 }
824}
825
826void
827ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
828{
829
830 MiscReg newVal = val;

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806}
807
808void
809ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
810{
811
812 MiscReg newVal = val;

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