isa.cc (11768:5b80960dcf08) isa.cc (11769:ec57caae355e)
1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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771 return (val);
772 }
773 case MISCREG_HDFAR: // alias for secure DFAR
774 return readMiscRegNoEffect(MISCREG_DFAR_S);
775 case MISCREG_HIFAR: // alias for secure IFAR
776 return readMiscRegNoEffect(MISCREG_IFAR_S);
777 case MISCREG_HVBAR: // bottom bits reserved
778 return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0;
1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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771 return (val);
772 }
773 case MISCREG_HDFAR: // alias for secure DFAR
774 return readMiscRegNoEffect(MISCREG_DFAR_S);
775 case MISCREG_HIFAR: // alias for secure IFAR
776 return readMiscRegNoEffect(MISCREG_IFAR_S);
777 case MISCREG_HVBAR: // bottom bits reserved
778 return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0;
779 case MISCREG_SCTLR: // Some bits hardwired
780 // The FI field (bit 21) is common between S/NS versions of the register
781 return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) |
782 (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; // V8 SCTLR
779 case MISCREG_SCTLR:
780 return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818;
783 case MISCREG_SCTLR_EL1:
781 case MISCREG_SCTLR_EL1:
784 // The FI field (bit 21) is common between S/NS versions of the register
785 return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) |
786 (readMiscRegNoEffect(misc_reg) & 0x37DDDBFF) | 0x30D00800; // V8 SCTLR_EL1
782 return (readMiscRegNoEffect(misc_reg) & 0x37DDDBFF) | 0x30D00800;
787 case MISCREG_SCTLR_EL3:
783 case MISCREG_SCTLR_EL3:
788 // The FI field (bit 21) is common between S/NS versions of the register
789 return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) |
790 (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; // V8 SCTLR_EL3
791 case MISCREG_HSCTLR: // FI comes from SCTLR
792 {
793 uint32_t mask = 1 << 27;
794 return (readMiscRegNoEffect(MISCREG_HSCTLR) & ~mask) |
795 (readMiscRegNoEffect(MISCREG_SCTLR) & mask);
796 }
784 return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830;
785 case MISCREG_HSCTLR:
786 return readMiscRegNoEffect(MISCREG_HSCTLR);
797
798 // Generic Timer registers
799 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
800 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
801 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
802 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
803 return getGenericTimer(tc).readMiscReg(misc_reg);
804

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1106 break;
1107 case MISCREG_SCR:
1108 tc->getITBPtr()->invalidateMiscReg();
1109 tc->getDTBPtr()->invalidateMiscReg();
1110 break;
1111 case MISCREG_SCTLR:
1112 {
1113 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
787
788 // Generic Timer registers
789 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
790 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
791 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
792 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
793 return getGenericTimer(tc).readMiscReg(misc_reg);
794

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1096 break;
1097 case MISCREG_SCR:
1098 tc->getITBPtr()->invalidateMiscReg();
1099 tc->getDTBPtr()->invalidateMiscReg();
1100 break;
1101 case MISCREG_SCTLR:
1102 {
1103 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
1114 MiscRegIndex sctlr_idx;
1115 scr = readMiscRegNoEffect(MISCREG_SCR);
1104 scr = readMiscRegNoEffect(MISCREG_SCR);
1116 if (haveSecurity && !scr.ns) {
1117 sctlr_idx = MISCREG_SCTLR_S;
1118 } else {
1119 sctlr_idx = MISCREG_SCTLR_NS;
1120 // The FI field (bit 21) is common between S/NS versions
1121 // of the register, we store this in the secure copy of
1122 // the reg
1123 miscRegs[MISCREG_SCTLR_S] &= ~(1 << 21);
1124 miscRegs[MISCREG_SCTLR_S] |= newVal & (1 << 21);
1125 }
1105 MiscRegIndex sctlr_idx = (haveSecurity && !scr.ns)
1106 ? MISCREG_SCTLR_S : MISCREG_SCTLR_NS;
1126 SCTLR sctlr = miscRegs[sctlr_idx];
1127 SCTLR new_sctlr = newVal;
1128 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization;
1129 miscRegs[sctlr_idx] = (MiscReg)new_sctlr;
1130 tc->getITBPtr()->invalidateMiscReg();
1131 tc->getDTBPtr()->invalidateMiscReg();
1132 }
1133 case MISCREG_MIDR:

--- 903 unchanged lines hidden --- 		1107 SCTLR sctlr = miscRegs[sctlr_idx];
1108 SCTLR new_sctlr = newVal;
1109 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization;
1110 miscRegs[sctlr_idx] = (MiscReg)new_sctlr;
1111 tc->getITBPtr()->invalidateMiscReg();
1112 tc->getDTBPtr()->invalidateMiscReg();
1113 }
1114 case MISCREG_MIDR:

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