isa.cc (11608:6319a1125f1c) isa.cc (11768:5b80960dcf08)
1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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51#include "sim/stat_control.hh"
52#include "sim/system.hh"
53
54namespace ArmISA
55{
56
57
58/**
1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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51#include "sim/stat_control.hh"
52#include "sim/system.hh"
53
54namespace ArmISA
55{
56
57
58/**
59 * Some registers aliase with others, and therefore need to be translated.
59 * Some registers alias with others, and therefore need to be translated.
60 * For each entry:
61 * The first value is the misc register that is to be looked up
62 * the second value is the lower part of the translation
63 * the third the upper part
60 * For each entry:
61 * The first value is the misc register that is to be looked up
62 * the second value is the lower part of the translation
63 * the third the upper part
64 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
64 */
65const struct ISA::MiscRegInitializerEntry
65 */
66const struct ISA::MiscRegInitializerEntry
66 ISA::MiscRegSwitch[miscRegTranslateMax] = {
67 {MISCREG_CSSELR_EL1, {MISCREG_CSSELR, 0}},
68 {MISCREG_SCTLR_EL1, {MISCREG_SCTLR, 0}},
69 {MISCREG_SCTLR_EL2, {MISCREG_HSCTLR, 0}},
70 {MISCREG_ACTLR_EL1, {MISCREG_ACTLR, 0}},
71 {MISCREG_ACTLR_EL2, {MISCREG_HACTLR, 0}},
67 ISA::MiscRegSwitch[] = {
68 {MISCREG_ACTLR_EL1, {MISCREG_ACTLR_NS, 0}},
69 {MISCREG_AFSR0_EL1, {MISCREG_ADFSR_NS, 0}},
70 {MISCREG_AFSR1_EL1, {MISCREG_AIFSR_NS, 0}},
71 {MISCREG_AMAIR_EL1, {MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS}},
72 {MISCREG_CONTEXTIDR_EL1, {MISCREG_CONTEXTIDR_NS, 0}},
72 {MISCREG_CPACR_EL1, {MISCREG_CPACR, 0}},
73 {MISCREG_CPACR_EL1, {MISCREG_CPACR, 0}},
73 {MISCREG_CPTR_EL2, {MISCREG_HCPTR, 0}},
74 {MISCREG_HCR_EL2, {MISCREG_HCR, 0}},
75 {MISCREG_MDCR_EL2, {MISCREG_HDCR, 0}},
76 {MISCREG_HSTR_EL2, {MISCREG_HSTR, 0}},
74 {MISCREG_CSSELR_EL1, {MISCREG_CSSELR_NS, 0}},
75 {MISCREG_DACR32_EL2, {MISCREG_DACR_NS, 0}},
76 {MISCREG_FAR_EL1, {MISCREG_DFAR_NS, MISCREG_IFAR_NS}},
77 // ESR_EL1 -> DFSR
77 {MISCREG_HACR_EL2, {MISCREG_HACR, 0}},
78 {MISCREG_HACR_EL2, {MISCREG_HACR, 0}},
78 {MISCREG_TTBR0_EL1, {MISCREG_TTBR0, 0}},
79 {MISCREG_TTBR1_EL1, {MISCREG_TTBR1, 0}},
80 {MISCREG_TTBR0_EL2, {MISCREG_HTTBR, 0}},
81 {MISCREG_VTTBR_EL2, {MISCREG_VTTBR, 0}},
82 {MISCREG_TCR_EL1, {MISCREG_TTBCR, 0}},
83 {MISCREG_TCR_EL2, {MISCREG_HTCR, 0}},
84 {MISCREG_VTCR_EL2, {MISCREG_VTCR, 0}},
85 {MISCREG_AFSR0_EL1, {MISCREG_ADFSR, 0}},
86 {MISCREG_AFSR1_EL1, {MISCREG_AIFSR, 0}},
79 {MISCREG_ACTLR_EL2, {MISCREG_HACTLR, 0}},
87 {MISCREG_AFSR0_EL2, {MISCREG_HADFSR, 0}},
88 {MISCREG_AFSR1_EL2, {MISCREG_HAIFSR, 0}},
80 {MISCREG_AFSR0_EL2, {MISCREG_HADFSR, 0}},
81 {MISCREG_AFSR1_EL2, {MISCREG_HAIFSR, 0}},
89 {MISCREG_ESR_EL2, {MISCREG_HSR, 0}},
90 {MISCREG_FAR_EL1, {MISCREG_DFAR, MISCREG_IFAR}},
82 {MISCREG_AMAIR_EL2, {MISCREG_HAMAIR0, MISCREG_HAMAIR1}},
83 {MISCREG_CPTR_EL2, {MISCREG_HCPTR, 0}},
84 {MISCREG_HCR_EL2, {MISCREG_HCR, 0 /*MISCREG_HCR2*/}},
85 {MISCREG_MDCR_EL2, {MISCREG_HDCR, 0}},
91 {MISCREG_FAR_EL2, {MISCREG_HDFAR, MISCREG_HIFAR}},
86 {MISCREG_FAR_EL2, {MISCREG_HDFAR, MISCREG_HIFAR}},
92 {MISCREG_HPFAR_EL2, {MISCREG_HPFAR, 0}},
93 {MISCREG_PAR_EL1, {MISCREG_PAR, 0}},
94 {MISCREG_MAIR_EL1, {MISCREG_PRRR, MISCREG_NMRR}},
95 {MISCREG_MAIR_EL2, {MISCREG_HMAIR0, MISCREG_HMAIR1}},
87 {MISCREG_MAIR_EL2, {MISCREG_HMAIR0, MISCREG_HMAIR1}},
96 {MISCREG_AMAIR_EL1, {MISCREG_AMAIR0, MISCREG_AMAIR1}},
97 {MISCREG_VBAR_EL1, {MISCREG_VBAR, 0}},
98 {MISCREG_VBAR_EL2, {MISCREG_HVBAR, 0}},
99 {MISCREG_CONTEXTIDR_EL1, {MISCREG_CONTEXTIDR, 0}},
100 {MISCREG_TPIDR_EL0, {MISCREG_TPIDRURW, 0}},
101 {MISCREG_TPIDRRO_EL0, {MISCREG_TPIDRURO, 0}},
102 {MISCREG_TPIDR_EL1, {MISCREG_TPIDRPRW, 0}},
88 {MISCREG_HPFAR_EL2, {MISCREG_HPFAR, 0}},
89 {MISCREG_SCTLR_EL2, {MISCREG_HSCTLR, 0}},
90 {MISCREG_ESR_EL2, {MISCREG_HSR, 0}},
91 {MISCREG_HSTR_EL2, {MISCREG_HSTR, 0}},
92 {MISCREG_TCR_EL2, {MISCREG_HTCR, 0}},
103 {MISCREG_TPIDR_EL2, {MISCREG_HTPIDR, 0}},
93 {MISCREG_TPIDR_EL2, {MISCREG_HTPIDR, 0}},
104 {MISCREG_TEECR32_EL1, {MISCREG_TEECR, 0}},
94 {MISCREG_TTBR0_EL2, {MISCREG_HTTBR, 0}},
95 {MISCREG_VBAR_EL2, {MISCREG_HVBAR, 0}},
96 {MISCREG_IFSR32_EL2, {MISCREG_IFSR_NS, 0}},
97 {MISCREG_MAIR_EL1, {MISCREG_PRRR_NS, MISCREG_NMRR_NS}},
98 {MISCREG_PAR_EL1, {MISCREG_PAR_NS, 0}},
99 // RMR_EL1 -> RMR
100 // RMR_EL2 -> HRMR
101 {MISCREG_SCTLR_EL1, {MISCREG_SCTLR_NS, 0}},
102 {MISCREG_SDER32_EL3, {MISCREG_SDER, 0}},
103 {MISCREG_TPIDR_EL1, {MISCREG_TPIDRPRW_NS, 0}},
104 {MISCREG_TPIDRRO_EL0, {MISCREG_TPIDRURO_NS, 0}},
105 {MISCREG_TPIDR_EL0, {MISCREG_TPIDRURW_NS, 0}},
106 {MISCREG_TCR_EL1, {MISCREG_TTBCR_NS, 0}},
107 {MISCREG_TTBR0_EL1, {MISCREG_TTBR0_NS, 0}},
108 {MISCREG_TTBR1_EL1, {MISCREG_TTBR1_NS, 0}},
109 {MISCREG_VBAR_EL1, {MISCREG_VBAR_NS, 0}},
110 {MISCREG_VMPIDR_EL2, {MISCREG_VMPIDR, 0}},
111 {MISCREG_VPIDR_EL2, {MISCREG_VPIDR, 0}},
112 {MISCREG_VTCR_EL2, {MISCREG_VTCR, 0}},
113 {MISCREG_VTTBR_EL2, {MISCREG_VTTBR, 0}},
105 {MISCREG_CNTFRQ_EL0, {MISCREG_CNTFRQ, 0}},
114 {MISCREG_CNTFRQ_EL0, {MISCREG_CNTFRQ, 0}},
106 {MISCREG_CNTPCT_EL0, {MISCREG_CNTPCT, 0}},
107 {MISCREG_CNTVCT_EL0, {MISCREG_CNTVCT, 0}},
108 {MISCREG_CNTVOFF_EL2, {MISCREG_CNTVOFF, 0}},
109 {MISCREG_CNTKCTL_EL1, {MISCREG_CNTKCTL, 0}},
110 {MISCREG_CNTHCTL_EL2, {MISCREG_CNTHCTL, 0}},
115 {MISCREG_CNTHCTL_EL2, {MISCREG_CNTHCTL, 0}},
111 {MISCREG_CNTP_TVAL_EL0, {MISCREG_CNTP_TVAL, 0}},
112 {MISCREG_CNTP_CTL_EL0, {MISCREG_CNTP_CTL, 0}},
113 {MISCREG_CNTP_CVAL_EL0, {MISCREG_CNTP_CVAL, 0}},
114 {MISCREG_CNTV_TVAL_EL0, {MISCREG_CNTV_TVAL, 0}},
115 {MISCREG_CNTV_CTL_EL0, {MISCREG_CNTV_CTL, 0}},
116 {MISCREG_CNTV_CVAL_EL0, {MISCREG_CNTV_CVAL, 0}},
117 {MISCREG_CNTHP_TVAL_EL2, {MISCREG_CNTHP_TVAL, 0}},
118 {MISCREG_CNTHP_CTL_EL2, {MISCREG_CNTHP_CTL, 0}},
116 {MISCREG_CNTHP_CTL_EL2, {MISCREG_CNTHP_CTL, 0}},
119 {MISCREG_CNTHP_CVAL_EL2, {MISCREG_CNTHP_CVAL, 0}},
120 {MISCREG_DACR32_EL2, {MISCREG_DACR, 0}},
121 {MISCREG_IFSR32_EL2, {MISCREG_IFSR, 0}},
122 {MISCREG_TEEHBR32_EL1, {MISCREG_TEEHBR, 0}},
123 {MISCREG_SDER32_EL3, {MISCREG_SDER, 0}}
117 {MISCREG_CNTHP_CVAL_EL2, {MISCREG_CNTHP_CVAL, 0}}, /* 64b */
118 {MISCREG_CNTHP_TVAL_EL2, {MISCREG_CNTHP_TVAL, 0}},
119 {MISCREG_CNTKCTL_EL1, {MISCREG_CNTKCTL, 0}},
120 {MISCREG_CNTP_CTL_EL0, {MISCREG_CNTP_CTL_NS, 0}},
121 {MISCREG_CNTP_CVAL_EL0, {MISCREG_CNTP_CVAL_NS, 0}}, /* 64b */
122 {MISCREG_CNTP_TVAL_EL0, {MISCREG_CNTP_TVAL_NS, 0}},
123 {MISCREG_CNTPCT_EL0, {MISCREG_CNTPCT, 0}}, /* 64b */
124 {MISCREG_CNTV_CTL_EL0, {MISCREG_CNTV_CTL, 0}},
125 {MISCREG_CNTV_CVAL_EL0, {MISCREG_CNTV_CVAL, 0}}, /* 64b */
126 {MISCREG_CNTV_TVAL_EL0, {MISCREG_CNTV_TVAL, 0}},
127 {MISCREG_CNTVCT_EL0, {MISCREG_CNTVCT, 0}}, /* 64b */
128 {MISCREG_CNTVOFF_EL2, {MISCREG_CNTVOFF, 0}}, /* 64b */
129 {MISCREG_DBGAUTHSTATUS_EL1, {MISCREG_DBGAUTHSTATUS, 0}},
130 {MISCREG_DBGBCR0_EL1, {MISCREG_DBGBCR0, 0}},
131 {MISCREG_DBGBCR1_EL1, {MISCREG_DBGBCR1, 0}},
132 {MISCREG_DBGBCR2_EL1, {MISCREG_DBGBCR2, 0}},
133 {MISCREG_DBGBCR3_EL1, {MISCREG_DBGBCR3, 0}},
134 {MISCREG_DBGBCR4_EL1, {MISCREG_DBGBCR4, 0}},
135 {MISCREG_DBGBCR5_EL1, {MISCREG_DBGBCR5, 0}},
136 {MISCREG_DBGBVR0_EL1, {MISCREG_DBGBVR0, 0 /* MISCREG_DBGBXVR0 */}},
137 {MISCREG_DBGBVR1_EL1, {MISCREG_DBGBVR1, 0 /* MISCREG_DBGBXVR1 */}},
138 {MISCREG_DBGBVR2_EL1, {MISCREG_DBGBVR2, 0 /* MISCREG_DBGBXVR2 */}},
139 {MISCREG_DBGBVR3_EL1, {MISCREG_DBGBVR3, 0 /* MISCREG_DBGBXVR3 */}},
140 {MISCREG_DBGBVR4_EL1, {MISCREG_DBGBVR4, MISCREG_DBGBXVR4}},
141 {MISCREG_DBGBVR5_EL1, {MISCREG_DBGBVR5, MISCREG_DBGBXVR5}},
142 {MISCREG_DBGCLAIMSET_EL1, {MISCREG_DBGCLAIMSET, 0}},
143 {MISCREG_DBGCLAIMCLR_EL1, {MISCREG_DBGCLAIMCLR, 0}},
144 // DBGDTR_EL0 -> DBGDTR{R or T}Xint
145 // DBGDTRRX_EL0 -> DBGDTRRXint
146 // DBGDTRTX_EL0 -> DBGDTRRXint
147 {MISCREG_DBGPRCR_EL1, {MISCREG_DBGPRCR, 0}},
148 {MISCREG_DBGVCR32_EL2, {MISCREG_DBGVCR, 0}},
149 {MISCREG_DBGWCR0_EL1, {MISCREG_DBGWCR0, 0}},
150 {MISCREG_DBGWCR1_EL1, {MISCREG_DBGWCR1, 0}},
151 {MISCREG_DBGWCR2_EL1, {MISCREG_DBGWCR2, 0}},
152 {MISCREG_DBGWCR3_EL1, {MISCREG_DBGWCR3, 0}},
153 {MISCREG_DBGWVR0_EL1, {MISCREG_DBGWVR0, 0}},
154 {MISCREG_DBGWVR1_EL1, {MISCREG_DBGWVR1, 0}},
155 {MISCREG_DBGWVR2_EL1, {MISCREG_DBGWVR2, 0}},
156 {MISCREG_DBGWVR3_EL1, {MISCREG_DBGWVR3, 0}},
157 {MISCREG_ID_DFR0_EL1, {MISCREG_ID_DFR0, 0}},
158 {MISCREG_MDCCSR_EL0, {MISCREG_DBGDSCRint, 0}},
159 {MISCREG_MDRAR_EL1, {MISCREG_DBGDRAR, 0}},
160 {MISCREG_MDSCR_EL1, {MISCREG_DBGDSCRext, 0}},
161 {MISCREG_OSDLR_EL1, {MISCREG_DBGOSDLR, 0}},
162 {MISCREG_OSDTRRX_EL1, {MISCREG_DBGDTRRXext, 0}},
163 {MISCREG_OSDTRTX_EL1, {MISCREG_DBGDTRTXext, 0}},
164 {MISCREG_OSECCR_EL1, {MISCREG_DBGOSECCR, 0}},
165 {MISCREG_OSLAR_EL1, {MISCREG_DBGOSLAR, 0}},
166 {MISCREG_OSLSR_EL1, {MISCREG_DBGOSLSR, 0}},
167 {MISCREG_PMCCNTR_EL0, {MISCREG_PMCCNTR, 0}},
168 {MISCREG_PMCEID0_EL0, {MISCREG_PMCEID0, 0}},
169 {MISCREG_PMCEID1_EL0, {MISCREG_PMCEID1, 0}},
170 {MISCREG_PMCNTENSET_EL0, {MISCREG_PMCNTENSET, 0}},
171 {MISCREG_PMCNTENCLR_EL0, {MISCREG_PMCNTENCLR, 0}},
172 {MISCREG_PMCR_EL0, {MISCREG_PMCR, 0}},
173/* {MISCREG_PMEVCNTR0_EL0, {MISCREG_PMEVCNTR0, 0}},
174 {MISCREG_PMEVCNTR1_EL0, {MISCREG_PMEVCNTR1, 0}},
175 {MISCREG_PMEVCNTR2_EL0, {MISCREG_PMEVCNTR2, 0}},
176 {MISCREG_PMEVCNTR3_EL0, {MISCREG_PMEVCNTR3, 0}},
177 {MISCREG_PMEVCNTR4_EL0, {MISCREG_PMEVCNTR4, 0}},
178 {MISCREG_PMEVCNTR5_EL0, {MISCREG_PMEVCNTR5, 0}},
179 {MISCREG_PMEVTYPER0_EL0, {MISCREG_PMEVTYPER0, 0}},
180 {MISCREG_PMEVTYPER1_EL0, {MISCREG_PMEVTYPER1, 0}},
181 {MISCREG_PMEVTYPER2_EL0, {MISCREG_PMEVTYPER2, 0}},
182 {MISCREG_PMEVTYPER3_EL0, {MISCREG_PMEVTYPER3, 0}},
183 {MISCREG_PMEVTYPER4_EL0, {MISCREG_PMEVTYPER4, 0}},
184 {MISCREG_PMEVTYPER5_EL0, {MISCREG_PMEVTYPER5, 0}}, */
185 {MISCREG_PMINTENCLR_EL1, {MISCREG_PMINTENCLR, 0}},
186 {MISCREG_PMINTENSET_EL1, {MISCREG_PMINTENSET, 0}},
187// {MISCREG_PMOVSCLR_EL0, {MISCREG_PMOVSCLR, 0}},
188 {MISCREG_PMOVSSET_EL0, {MISCREG_PMOVSSET, 0}},
189 {MISCREG_PMSELR_EL0, {MISCREG_PMSELR, 0}},
190 {MISCREG_PMSWINC_EL0, {MISCREG_PMSWINC, 0}},
191 {MISCREG_PMUSERENR_EL0, {MISCREG_PMUSERENR, 0}},
192 {MISCREG_PMXEVCNTR_EL0, {MISCREG_PMXEVCNTR, 0}},
193 {MISCREG_PMXEVTYPER_EL0, {MISCREG_PMXEVTYPER, 0}},
194
195 // from ARM DDI 0487A.i, template text
196 // "AArch64 System register ___ can be mapped to
197 // AArch32 System register ___, but this is not
198 // architecturally mandated."
199 {MISCREG_SCR_EL3, {MISCREG_SCR, 0}}, // D7-2005
200 // MDCR_EL3 -> SDCR, D7-2108 (the latter is unimpl. in gem5)
201 {MISCREG_SPSR_EL1, {MISCREG_SPSR_SVC, 0}}, // C5.2.17 SPSR_EL1
202 {MISCREG_SPSR_EL2, {MISCREG_SPSR_HYP, 0}}, // C5.2.18 SPSR_EL2
203 {MISCREG_SPSR_EL3, {MISCREG_SPSR_MON, 0}}, // C5.2.19 SPSR_EL3
124};
125
126
127ISA::ISA(Params *p)
128 : SimObject(p),
129 system(NULL),
130 _decoderFlavour(p->decoderFlavour),
131 pmu(p->pmu),

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155 physAddrRange64 = system->physAddrRange64();
156 } else {
157 haveSecurity = haveLPAE = haveVirtualization = false;
158 haveLargeAsid64 = false;
159 physAddrRange64 = 32; // dummy value
160 }
161
162 /** Fill in the miscReg translation table */
204};
205
206
207ISA::ISA(Params *p)
208 : SimObject(p),
209 system(NULL),
210 _decoderFlavour(p->decoderFlavour),
211 pmu(p->pmu),

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235 physAddrRange64 = system->physAddrRange64();
236 } else {
237 haveSecurity = haveLPAE = haveVirtualization = false;
238 haveLargeAsid64 = false;
239 physAddrRange64 = 32; // dummy value
240 }
241
242 /** Fill in the miscReg translation table */
163 for (uint32_t i = 0; i < miscRegTranslateMax; i++) {
164 struct MiscRegLUTEntry new_entry;
165
166 uint32_t select = MiscRegSwitch[i].index;
167 new_entry = MiscRegSwitch[i].entry;
168
169 lookUpMiscReg[select] = new_entry;
243 for (auto sw : MiscRegSwitch) {
244 lookUpMiscReg[sw.index] = sw.entry;
170 }
171
172 preUnflattenMiscReg();
173
174 clear();
175}
176
177const ArmISAParams *

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714 return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) |
715 (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; // V8 SCTLR_EL3
716 case MISCREG_HSCTLR: // FI comes from SCTLR
717 {
718 uint32_t mask = 1 << 27;
719 return (readMiscRegNoEffect(MISCREG_HSCTLR) & ~mask) |
720 (readMiscRegNoEffect(MISCREG_SCTLR) & mask);
721 }
245 }
246
247 preUnflattenMiscReg();
248
249 clear();
250}
251
252const ArmISAParams *

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789 return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) |
790 (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; // V8 SCTLR_EL3
791 case MISCREG_HSCTLR: // FI comes from SCTLR
792 {
793 uint32_t mask = 1 << 27;
794 return (readMiscRegNoEffect(MISCREG_HSCTLR) & ~mask) |
795 (readMiscRegNoEffect(MISCREG_SCTLR) & mask);
796 }
722 case MISCREG_SCR:
723 {
724 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
725 if (cpsr.width) {
726 return readMiscRegNoEffect(MISCREG_SCR);
727 } else {
728 return readMiscRegNoEffect(MISCREG_SCR_EL3);
729 }
730 }
731
732 // Generic Timer registers
733 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
734 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
735 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
736 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
737 return getGenericTimer(tc).readMiscReg(misc_reg);
738

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798 // Generic Timer registers
799 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
800 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
801 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
802 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
803 return getGenericTimer(tc).readMiscReg(misc_reg);
804

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