isa.cc (11584:bbd8448f104e) isa.cc (11608:6319a1125f1c)
1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 1451 unchanged lines hidden (view full) ---

1460 case MISCREG_ATS1CUW:
1461 case MISCREG_ATS12NSOPR:
1462 case MISCREG_ATS12NSOPW:
1463 case MISCREG_ATS12NSOUR:
1464 case MISCREG_ATS12NSOUW:
1465 case MISCREG_ATS1HR:
1466 case MISCREG_ATS1HW:
1467 {
1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 1451 unchanged lines hidden (view full) ---

1460 case MISCREG_ATS1CUW:
1461 case MISCREG_ATS12NSOPR:
1462 case MISCREG_ATS12NSOPW:
1463 case MISCREG_ATS12NSOUR:
1464 case MISCREG_ATS12NSOUW:
1465 case MISCREG_ATS1HR:
1466 case MISCREG_ATS1HW:
1467 {
1468 unsigned flags = 0;
1468 Request::Flags flags = 0;
1469 BaseTLB::Mode mode = BaseTLB::Read;
1470 TLB::ArmTranslationType tranType = TLB::NormalTran;
1471 Fault fault;
1472 switch(misc_reg) {
1473 case MISCREG_ATS1CPR:
1474 flags = TLB::MustBeOne;
1475 tranType = TLB::S1CTran;
1476 mode = BaseTLB::Read;

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1705 case MISCREG_AT_S12E1R_Xt:
1706 case MISCREG_AT_S12E1W_Xt:
1707 case MISCREG_AT_S12E0R_Xt:
1708 case MISCREG_AT_S12E0W_Xt:
1709 case MISCREG_AT_S1E3R_Xt:
1710 case MISCREG_AT_S1E3W_Xt:
1711 {
1712 RequestPtr req = new Request;
1469 BaseTLB::Mode mode = BaseTLB::Read;
1470 TLB::ArmTranslationType tranType = TLB::NormalTran;
1471 Fault fault;
1472 switch(misc_reg) {
1473 case MISCREG_ATS1CPR:
1474 flags = TLB::MustBeOne;
1475 tranType = TLB::S1CTran;
1476 mode = BaseTLB::Read;

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1705 case MISCREG_AT_S12E1R_Xt:
1706 case MISCREG_AT_S12E1W_Xt:
1707 case MISCREG_AT_S12E0R_Xt:
1708 case MISCREG_AT_S12E0W_Xt:
1709 case MISCREG_AT_S1E3R_Xt:
1710 case MISCREG_AT_S1E3W_Xt:
1711 {
1712 RequestPtr req = new Request;
1713 unsigned flags = 0;
1713 Request::Flags flags = 0;
1714 BaseTLB::Mode mode = BaseTLB::Read;
1715 TLB::ArmTranslationType tranType = TLB::NormalTran;
1716 Fault fault;
1717 switch(misc_reg) {
1718 case MISCREG_AT_S1E1R_Xt:
1719 flags = TLB::MustBeOne;
1720 tranType = TLB::S1E1Tran;
1721 mode = BaseTLB::Read;

--- 249 unchanged lines hidden --- 		1714 BaseTLB::Mode mode = BaseTLB::Read;
1715 TLB::ArmTranslationType tranType = TLB::NormalTran;
1716 Fault fault;
1717 switch(misc_reg) {
1718 case MISCREG_AT_S1E1R_Xt:
1719 flags = TLB::MustBeOne;
1720 tranType = TLB::S1E1Tran;
1721 mode = BaseTLB::Read;

--- 249 unchanged lines hidden ---