isa.cc (11575:0005b28685f0) isa.cc (11577:a26a328c20eb)
1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 1684 unchanged lines hidden (view full) ---

1693 RequestPtr req = new Request;
1694 unsigned flags = 0;
1695 BaseTLB::Mode mode = BaseTLB::Read;
1696 TLB::ArmTranslationType tranType = TLB::NormalTran;
1697 Fault fault;
1698 switch(misc_reg) {
1699 case MISCREG_AT_S1E1R_Xt:
1700 flags = TLB::MustBeOne;
1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 1684 unchanged lines hidden (view full) ---

1693 RequestPtr req = new Request;
1694 unsigned flags = 0;
1695 BaseTLB::Mode mode = BaseTLB::Read;
1696 TLB::ArmTranslationType tranType = TLB::NormalTran;
1697 Fault fault;
1698 switch(misc_reg) {
1699 case MISCREG_AT_S1E1R_Xt:
1700 flags = TLB::MustBeOne;
1701 tranType = TLB::S1CTran;
1701 tranType = TLB::S1E1Tran;
1702 mode = BaseTLB::Read;
1703 break;
1704 case MISCREG_AT_S1E1W_Xt:
1705 flags = TLB::MustBeOne;
1702 mode = BaseTLB::Read;
1703 break;
1704 case MISCREG_AT_S1E1W_Xt:
1705 flags = TLB::MustBeOne;
1706 tranType = TLB::S1CTran;
1706 tranType = TLB::S1E1Tran;
1707 mode = BaseTLB::Write;
1708 break;
1709 case MISCREG_AT_S1E0R_Xt:
1710 flags = TLB::MustBeOne | TLB::UserMode;
1707 mode = BaseTLB::Write;
1708 break;
1709 case MISCREG_AT_S1E0R_Xt:
1710 flags = TLB::MustBeOne | TLB::UserMode;
1711 tranType = TLB::S1CTran;
1711 tranType = TLB::S1E0Tran;
1712 mode = BaseTLB::Read;
1713 break;
1714 case MISCREG_AT_S1E0W_Xt:
1715 flags = TLB::MustBeOne | TLB::UserMode;
1712 mode = BaseTLB::Read;
1713 break;
1714 case MISCREG_AT_S1E0W_Xt:
1715 flags = TLB::MustBeOne | TLB::UserMode;
1716 tranType = TLB::S1CTran;
1716 tranType = TLB::S1E0Tran;
1717 mode = BaseTLB::Write;
1718 break;
1719 case MISCREG_AT_S1E2R_Xt:
1720 flags = TLB::MustBeOne;
1717 mode = BaseTLB::Write;
1718 break;
1719 case MISCREG_AT_S1E2R_Xt:
1720 flags = TLB::MustBeOne;
1721 tranType = TLB::HypMode;
1721 tranType = TLB::S1E2Tran;
1722 mode = BaseTLB::Read;
1723 break;
1724 case MISCREG_AT_S1E2W_Xt:
1725 flags = TLB::MustBeOne;
1722 mode = BaseTLB::Read;
1723 break;
1724 case MISCREG_AT_S1E2W_Xt:
1725 flags = TLB::MustBeOne;
1726 tranType = TLB::HypMode;
1726 tranType = TLB::S1E2Tran;
1727 mode = BaseTLB::Write;
1728 break;
1729 case MISCREG_AT_S12E0R_Xt:
1730 flags = TLB::MustBeOne | TLB::UserMode;
1727 mode = BaseTLB::Write;
1728 break;
1729 case MISCREG_AT_S12E0R_Xt:
1730 flags = TLB::MustBeOne | TLB::UserMode;
1731 tranType = TLB::S1S2NsTran;
1731 tranType = TLB::S12E0Tran;
1732 mode = BaseTLB::Read;
1733 break;
1734 case MISCREG_AT_S12E0W_Xt:
1735 flags = TLB::MustBeOne | TLB::UserMode;
1732 mode = BaseTLB::Read;
1733 break;
1734 case MISCREG_AT_S12E0W_Xt:
1735 flags = TLB::MustBeOne | TLB::UserMode;
1736 tranType = TLB::S1S2NsTran;
1736 tranType = TLB::S12E0Tran;
1737 mode = BaseTLB::Write;
1738 break;
1739 case MISCREG_AT_S12E1R_Xt:
1740 flags = TLB::MustBeOne;
1737 mode = BaseTLB::Write;
1738 break;
1739 case MISCREG_AT_S12E1R_Xt:
1740 flags = TLB::MustBeOne;
1741 tranType = TLB::S1S2NsTran;
1741 tranType = TLB::S12E1Tran;
1742 mode = BaseTLB::Read;
1743 break;
1744 case MISCREG_AT_S12E1W_Xt:
1745 flags = TLB::MustBeOne;
1742 mode = BaseTLB::Read;
1743 break;
1744 case MISCREG_AT_S12E1W_Xt:
1745 flags = TLB::MustBeOne;
1746 tranType = TLB::S1S2NsTran;
1746 tranType = TLB::S12E1Tran;
1747 mode = BaseTLB::Write;
1748 break;
1749 case MISCREG_AT_S1E3R_Xt:
1750 flags = TLB::MustBeOne;
1747 mode = BaseTLB::Write;
1748 break;
1749 case MISCREG_AT_S1E3R_Xt:
1750 flags = TLB::MustBeOne;
1751 tranType = TLB::HypMode; // There is no TZ mode defined.
1751 tranType = TLB::S1E3Tran;
1752 mode = BaseTLB::Read;
1753 break;
1754 case MISCREG_AT_S1E3W_Xt:
1755 flags = TLB::MustBeOne;
1752 mode = BaseTLB::Read;
1753 break;
1754 case MISCREG_AT_S1E3W_Xt:
1755 flags = TLB::MustBeOne;
1756 tranType = TLB::HypMode; // There is no TZ mode defined.
1756 tranType = TLB::S1E3Tran;
1757 mode = BaseTLB::Write;
1758 break;
1759 }
1760 // If we're in timing mode then doing the translation in
1761 // functional mode then we're slightly distorting performance
1762 // results obtained from simulations. The translation should be
1763 // done in the same mode the core is running in. NOTE: This
1764 // can't be an atomic translation because that causes problems

--- 18 unchanged lines hidden (view full) ---

1783 DPRINTF(MiscRegs,
1784 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
1785 val, newVal);
1786 } else {
1787 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get());
1788 // Set fault bit and FSR
1789 FSR fsr = armFault->getFsr(tc);
1790
1757 mode = BaseTLB::Write;
1758 break;
1759 }
1760 // If we're in timing mode then doing the translation in
1761 // functional mode then we're slightly distorting performance
1762 // results obtained from simulations. The translation should be
1763 // done in the same mode the core is running in. NOTE: This
1764 // can't be an atomic translation because that causes problems

--- 18 unchanged lines hidden (view full) ---

1783 DPRINTF(MiscRegs,
1784 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
1785 val, newVal);
1786 } else {
1787 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get());
1788 // Set fault bit and FSR
1789 FSR fsr = armFault->getFsr(tc);
1790
1791 newVal = ((fsr >> 9) & 1) << 11;
1792 // rearange fault status
1793 newVal |= ((fsr >> 0) & 0x3f) << 1;
1794 newVal |= 0x1; // F bit
1795 newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1796 newVal |= armFault->isStage2() ? 0x200 : 0;
1791 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
1792 if (cpsr.width) { // AArch32
1793 newVal = ((fsr >> 9) & 1) << 11;
1794 // rearrange fault status
1795 newVal |= ((fsr >> 0) & 0x3f) << 1;
1796 newVal |= 0x1; // F bit
1797 newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1798 newVal |= armFault->isStage2() ? 0x200 : 0;
1799 } else { // AArch64
1800 newVal = 1; // F bit
1801 newVal |= fsr << 1; // FST
1802 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit.
1803 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW
1804 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S
1805 newVal |= 1 << 11; // RES1
1806 }
1797 DPRINTF(MiscRegs,
1798 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
1799 val, fsr, newVal);
1800 }
1801 delete req;
1802 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal);
1803 return;
1804 }

--- 137 unchanged lines hidden --- 		1807 DPRINTF(MiscRegs,
1808 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
1809 val, fsr, newVal);
1810 }
1811 delete req;
1812 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal);
1813 return;
1814 }

--- 137 unchanged lines hidden ---