isa.cc (10609:ae5582819481) isa.cc (10653:e3fc6bc7f97e)
1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1485 case MISCREG_ATS1CUW:
1486 case MISCREG_ATS12NSOPR:
1487 case MISCREG_ATS12NSOPW:
1488 case MISCREG_ATS12NSOUR:
1489 case MISCREG_ATS12NSOUW:
1490 case MISCREG_ATS1HR:
1491 case MISCREG_ATS1HW:
1492 {
1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1485 case MISCREG_ATS1CUW:
1486 case MISCREG_ATS12NSOPR:
1487 case MISCREG_ATS12NSOPW:
1488 case MISCREG_ATS12NSOUR:
1489 case MISCREG_ATS12NSOUW:
1490 case MISCREG_ATS1HR:
1491 case MISCREG_ATS1HW:
1492 {
1493 RequestPtr req = new Request;
1494 unsigned flags = 0;
1495 BaseTLB::Mode mode = BaseTLB::Read;
1496 TLB::ArmTranslationType tranType = TLB::NormalTran;
1497 Fault fault;
1498 switch(misc_reg) {
1499 case MISCREG_ATS1CPR:
1500 flags = TLB::MustBeOne;
1501 tranType = TLB::S1CTran;

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1557 }
1558 // If we're in timing mode then doing the translation in
1559 // functional mode then we're slightly distorting performance
1560 // results obtained from simulations. The translation should be
1561 // done in the same mode the core is running in. NOTE: This
1562 // can't be an atomic translation because that causes problems
1563 // with unexpected atomic snoop requests.
1564 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
1493 unsigned flags = 0;
1494 BaseTLB::Mode mode = BaseTLB::Read;
1495 TLB::ArmTranslationType tranType = TLB::NormalTran;
1496 Fault fault;
1497 switch(misc_reg) {
1498 case MISCREG_ATS1CPR:
1499 flags = TLB::MustBeOne;
1500 tranType = TLB::S1CTran;

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1556 }
1557 // If we're in timing mode then doing the translation in
1558 // functional mode then we're slightly distorting performance
1559 // results obtained from simulations. The translation should be
1560 // done in the same mode the core is running in. NOTE: This
1561 // can't be an atomic translation because that causes problems
1562 // with unexpected atomic snoop requests.
1563 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
1565 req->setVirt(0, val, 1, flags, Request::funcMasterId,
1566 tc->pcState().pc());
1567 req->setThreadContext(tc->contextId(), tc->threadId());
1568 fault = tc->getDTBPtr()->translateFunctional(req, tc, mode, tranType);
1564 Request req(0, val, 1, flags, Request::funcMasterId,
1565 tc->pcState().pc(), tc->contextId(),
1566 tc->threadId());
1567 fault = tc->getDTBPtr()->translateFunctional(&req, tc, mode, tranType);
1569 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1570 HCR hcr = readMiscRegNoEffect(MISCREG_HCR);
1571
1572 MiscReg newVal;
1573 if (fault == NoFault) {
1568 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1569 HCR hcr = readMiscRegNoEffect(MISCREG_HCR);
1570
1571 MiscReg newVal;
1572 if (fault == NoFault) {
1574 Addr paddr = req->getPaddr();
1573 Addr paddr = req.getPaddr();
1575 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode ||
1576 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) {
1577 newVal = (paddr & mask(39, 12)) |
1578 (tc->getDTBPtr()->getAttr());
1579 } else {
1580 newVal = (paddr & 0xfffff000) |
1581 (tc->getDTBPtr()->getAttr());
1582 }

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1600 }
1601 newVal |= 0x1; // F bit
1602 newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1603 newVal |= armFault->isStage2() ? 0x200 : 0;
1604 DPRINTF(MiscRegs,
1605 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
1606 val, fsr, newVal);
1607 }
1574 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode ||
1575 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) {
1576 newVal = (paddr & mask(39, 12)) |
1577 (tc->getDTBPtr()->getAttr());
1578 } else {
1579 newVal = (paddr & 0xfffff000) |
1580 (tc->getDTBPtr()->getAttr());
1581 }

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1599 }
1600 newVal |= 0x1; // F bit
1601 newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1602 newVal |= armFault->isStage2() ? 0x200 : 0;
1603 DPRINTF(MiscRegs,
1604 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
1605 val, fsr, newVal);
1606 }
1608 delete req;
1609 setMiscRegNoEffect(MISCREG_PAR, newVal);
1610 return;
1611 }
1612 case MISCREG_TTBCR:
1613 {
1614 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1615 const uint32_t ones = (uint32_t)(-1);
1616 TTBCR ttbcrMask = 0;

--- 445 unchanged lines hidden --- 		1607 setMiscRegNoEffect(MISCREG_PAR, newVal);
1608 return;
1609 }
1610 case MISCREG_TTBCR:
1611 {
1612 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1613 const uint32_t ones = (uint32_t)(-1);
1614 TTBCR ttbcrMask = 0;

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