isa.cc (10461:afeb5cdb3907) isa.cc (10508:aa46a8ae3487)
1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1096 }
1097 SCTLR sctlr = miscRegs[sctlr_idx];
1098 SCTLR new_sctlr = newVal;
1099 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization;
1100 miscRegs[sctlr_idx] = (MiscReg)new_sctlr;
1101 tc->getITBPtr()->invalidateMiscReg();
1102 tc->getDTBPtr()->invalidateMiscReg();
1103
1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1096 }
1097 SCTLR sctlr = miscRegs[sctlr_idx];
1098 SCTLR new_sctlr = newVal;
1099 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization;
1100 miscRegs[sctlr_idx] = (MiscReg)new_sctlr;
1101 tc->getITBPtr()->invalidateMiscReg();
1102 tc->getDTBPtr()->invalidateMiscReg();
1103
1104 // Check if all CPUs are booted with caches enabled
1105 // so we can stop enforcing coherency of some kernel
1106 // structures manually.
1107 sys = tc->getSystemPtr();
1108 for (x = 0; x < sys->numContexts(); x++) {
1109 oc = sys->getThreadContext(x);
1110 // @todo: double check this for security
1111 SCTLR other_sctlr = oc->readMiscRegNoEffect(MISCREG_SCTLR);
1112 if (!other_sctlr.c && oc->status() != ThreadContext::Halted)
1113 return;
1114 }
1115
1116 for (x = 0; x < sys->numContexts(); x++) {
1117 oc = sys->getThreadContext(x);
1118 oc->getDTBPtr()->allCpusCaching();
1119 oc->getITBPtr()->allCpusCaching();
1120
1121 // If CheckerCPU is connected, need to notify it.
1122 CheckerCPU *checker = oc->getCheckerCpuPtr();
1123 if (checker) {
1124 checker->getDTBPtr()->allCpusCaching();
1125 checker->getITBPtr()->allCpusCaching();
1126 }
1127 }
1104 if (new_sctlr.c)
1105 updateBootUncacheable(sctlr_idx, tc);
1128 return;
1129 }
1106 return;
1107 }
1130
1131 case MISCREG_MIDR:
1132 case MISCREG_ID_PFR0:
1133 case MISCREG_ID_PFR1:
1134 case MISCREG_ID_DFR0:
1135 case MISCREG_ID_MMFR0:
1136 case MISCREG_ID_MMFR1:
1137 case MISCREG_ID_MMFR2:
1138 case MISCREG_ID_MMFR3:

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1669 if (ttbcr.eae) {
1670 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
1671 // ARMv8 AArch32 bit 63-56 only
1672 uint64_t ttbrMask = mask(63,56) | mask(47,40);
1673 newVal = (newVal & (~ttbrMask));
1674 }
1675 }
1676 }
1108 case MISCREG_MIDR:
1109 case MISCREG_ID_PFR0:
1110 case MISCREG_ID_PFR1:
1111 case MISCREG_ID_DFR0:
1112 case MISCREG_ID_MMFR0:
1113 case MISCREG_ID_MMFR1:
1114 case MISCREG_ID_MMFR2:
1115 case MISCREG_ID_MMFR3:

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1646 if (ttbcr.eae) {
1647 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
1648 // ARMv8 AArch32 bit 63-56 only
1649 uint64_t ttbrMask = mask(63,56) | mask(47,40);
1650 newVal = (newVal & (~ttbrMask));
1651 }
1652 }
1653 }
1654 case MISCREG_SCTLR_EL1:
1655 {
1656 tc->getITBPtr()->invalidateMiscReg();
1657 tc->getDTBPtr()->invalidateMiscReg();
1658 SCTLR new_sctlr = newVal;
1659 setMiscRegNoEffect(misc_reg, newVal);
1660 if (new_sctlr.c)
1661 updateBootUncacheable(misc_reg, tc);
1662 return;
1663 }
1677 case MISCREG_CONTEXTIDR:
1678 case MISCREG_PRRR:
1679 case MISCREG_NMRR:
1680 case MISCREG_MAIR0:
1681 case MISCREG_MAIR1:
1682 case MISCREG_DACR:
1683 case MISCREG_VTTBR:
1684 case MISCREG_SCR_EL3:
1664 case MISCREG_CONTEXTIDR:
1665 case MISCREG_PRRR:
1666 case MISCREG_NMRR:
1667 case MISCREG_MAIR0:
1668 case MISCREG_MAIR1:
1669 case MISCREG_DACR:
1670 case MISCREG_VTTBR:
1671 case MISCREG_SCR_EL3:
1685 case MISCREG_SCTLR_EL1:
1686 case MISCREG_SCTLR_EL2:
1687 case MISCREG_SCTLR_EL3:
1688 case MISCREG_TCR_EL1:
1689 case MISCREG_TCR_EL2:
1690 case MISCREG_TCR_EL3:
1672 case MISCREG_TCR_EL1:
1673 case MISCREG_TCR_EL2:
1674 case MISCREG_TCR_EL3:
1675 case MISCREG_SCTLR_EL2:
1676 case MISCREG_SCTLR_EL3:
1691 case MISCREG_TTBR0_EL1:
1692 case MISCREG_TTBR1_EL1:
1693 case MISCREG_TTBR0_EL2:
1694 case MISCREG_TTBR0_EL3:
1695 tc->getITBPtr()->invalidateMiscReg();
1696 tc->getDTBPtr()->invalidateMiscReg();
1697 break;
1698 case MISCREG_NZCV:

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1917 // case MISCREG_CNTV_CTL_EL2:
1918 break;
1919 }
1920 }
1921 setMiscRegNoEffect(misc_reg, newVal);
1922}
1923
1924void
1677 case MISCREG_TTBR0_EL1:
1678 case MISCREG_TTBR1_EL1:
1679 case MISCREG_TTBR0_EL2:
1680 case MISCREG_TTBR0_EL3:
1681 tc->getITBPtr()->invalidateMiscReg();
1682 tc->getDTBPtr()->invalidateMiscReg();
1683 break;
1684 case MISCREG_NZCV:

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1903 // case MISCREG_CNTV_CTL_EL2:
1904 break;
1905 }
1906 }
1907 setMiscRegNoEffect(misc_reg, newVal);
1908}
1909
1910void
1911ISA::updateBootUncacheable(int sctlr_idx, ThreadContext *tc)
1912{
1913 System *sys;
1914 ThreadContext *oc;
1915
1916 // Check if all CPUs are booted with caches enabled
1917 // so we can stop enforcing coherency of some kernel
1918 // structures manually.
1919 sys = tc->getSystemPtr();
1920 for (int x = 0; x < sys->numContexts(); x++) {
1921 oc = sys->getThreadContext(x);
1922 // @todo: double check this for security
1923 SCTLR other_sctlr = oc->readMiscRegNoEffect(sctlr_idx);
1924 if (!other_sctlr.c && oc->status() != ThreadContext::Halted)
1925 return;
1926 }
1927
1928 for (int x = 0; x < sys->numContexts(); x++) {
1929 oc = sys->getThreadContext(x);
1930 oc->getDTBPtr()->allCpusCaching();
1931 oc->getITBPtr()->allCpusCaching();
1932
1933 // If CheckerCPU is connected, need to notify it.
1934 CheckerCPU *checker = oc->getCheckerCpuPtr();
1935 if (checker) {
1936 checker->getDTBPtr()->allCpusCaching();
1937 checker->getITBPtr()->allCpusCaching();
1938 }
1939 }
1940}
1941
1942void
1925ISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint8_t asid, bool secure_lookup,
1926 uint8_t target_el)
1927{
1928 if (haveLargeAsid64)
1929 asid &= mask(8);
1930 Addr va = ((Addr) bits(newVal, 43, 0)) << 12;
1931 System *sys = tc->getSystemPtr();
1932 for (int x = 0; x < sys->numContexts(); x++) {

--- 108 unchanged lines hidden --- 		1943ISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint8_t asid, bool secure_lookup,
1944 uint8_t target_el)
1945{
1946 if (haveLargeAsid64)
1947 asid &= mask(8);
1948 Addr va = ((Addr) bits(newVal, 43, 0)) << 12;
1949 System *sys = tc->getSystemPtr();
1950 for (int x = 0; x < sys->numContexts(); x++) {

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