isa.cc (10338:8bee5f4edb92) isa.cc (10461:afeb5cdb3907)
1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "arch/arm/pmu.hh"
42#include "arch/arm/system.hh"
43#include "cpu/checker/cpu.hh"
43#include "arch/arm/system.hh"
44#include "cpu/checker/cpu.hh"
45#include "cpu/base.hh"
44#include "debug/Arm.hh"
45#include "debug/MiscRegs.hh"
46#include "params/ArmISA.hh"
47#include "sim/faults.hh"
48#include "sim/stat_control.hh"
49#include "sim/system.hh"
50
51namespace ArmISA

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117 {MISCREG_DACR32_EL2, {MISCREG_DACR, 0}},
118 {MISCREG_IFSR32_EL2, {MISCREG_IFSR, 0}},
119 {MISCREG_TEEHBR32_EL1, {MISCREG_TEEHBR, 0}},
120 {MISCREG_SDER32_EL3, {MISCREG_SDER, 0}}
121};
122
123
124ISA::ISA(Params *p)
46#include "debug/Arm.hh"
47#include "debug/MiscRegs.hh"
48#include "params/ArmISA.hh"
49#include "sim/faults.hh"
50#include "sim/stat_control.hh"
51#include "sim/system.hh"
52
53namespace ArmISA

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119 {MISCREG_DACR32_EL2, {MISCREG_DACR, 0}},
120 {MISCREG_IFSR32_EL2, {MISCREG_IFSR, 0}},
121 {MISCREG_TEEHBR32_EL1, {MISCREG_TEEHBR, 0}},
122 {MISCREG_SDER32_EL3, {MISCREG_SDER, 0}}
123};
124
125
126ISA::ISA(Params *p)
125 : SimObject(p), system(NULL), lookUpMiscReg(NUM_MISCREGS, {0,0})
127 : SimObject(p),
128 system(NULL),
129 pmu(p->pmu),
130 lookUpMiscReg(NUM_MISCREGS, {0,0})
126{
127 SCTLR sctlr;
128 sctlr = 0;
129 miscRegs[MISCREG_SCTLR_RST] = sctlr;
130
131{
132 SCTLR sctlr;
133 sctlr = 0;
134 miscRegs[MISCREG_SCTLR_RST] = sctlr;
135
136 // Hook up a dummy device if we haven't been configured with a
137 // real PMU. By using a dummy device, we don't need to check that
138 // the PMU exist every time we try to access a PMU register.
139 if (!pmu)
140 pmu = &dummyDevice;
141
131 system = dynamic_cast<ArmSystem *>(p->system);
132 DPRINTFN("ISA system set to: %p %p\n", system, p->system);
133
134 // Cache system-level properties
135 if (FullSystem && system) {
136 haveSecurity = system->haveSecurity();
137 haveLPAE = system->haveLPAE();
138 haveVirtualization = system->haveVirtualization();

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351 miscRegs[MISCREG_SCTLR_EL1] = 0x30c50870;
352 // Always non-secure
353 miscRegs[MISCREG_SCR_EL3] = 1;
354 }
355
356 // Initialize configurable id registers
357 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1;
358 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1;
142 system = dynamic_cast<ArmSystem *>(p->system);
143 DPRINTFN("ISA system set to: %p %p\n", system, p->system);
144
145 // Cache system-level properties
146 if (FullSystem && system) {
147 haveSecurity = system->haveSecurity();
148 haveLPAE = system->haveLPAE();
149 haveVirtualization = system->haveVirtualization();

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362 miscRegs[MISCREG_SCTLR_EL1] = 0x30c50870;
363 // Always non-secure
364 miscRegs[MISCREG_SCR_EL3] = 1;
365 }
366
367 // Initialize configurable id registers
368 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1;
369 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1;
359 miscRegs[MISCREG_ID_AA64DFR0_EL1] = p->id_aa64dfr0_el1;
370 miscRegs[MISCREG_ID_AA64DFR0_EL1] =
371 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
372 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3
373
360 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1;
361 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1;
362 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1;
363 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1;
364 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1;
365 miscRegs[MISCREG_ID_AA64PFR0_EL1] = p->id_aa64pfr0_el1;
366 miscRegs[MISCREG_ID_AA64PFR1_EL1] = p->id_aa64pfr1_el1;
367
374 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1;
375 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1;
376 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1;
377 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1;
378 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1;
379 miscRegs[MISCREG_ID_AA64PFR0_EL1] = p->id_aa64pfr0_el1;
380 miscRegs[MISCREG_ID_AA64PFR1_EL1] = p->id_aa64pfr1_el1;
381
382 miscRegs[MISCREG_ID_DFR0_EL1] =
383 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3
384
385 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1];
386
368 // Enforce consistency with system-level settings...
369
370 // EL3
371 // (no AArch32/64 interprocessing support for now)
372 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
373 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
374 haveSecurity ? 0x1 : 0x0);
375 // EL2

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486 break;
487 case MISCREG_MPIDR_EL1:
488 // @todo in the absence of v8 virtualization support just return MPIDR_EL1
489 return getMPIDR(system, tc) & 0xffffffff;
490 case MISCREG_VMPIDR:
491 // top bit defined as RES1
492 return readMiscRegNoEffect(misc_reg) | 0x80000000;
493 case MISCREG_ID_AFR0: // not implemented, so alias MIDR
387 // Enforce consistency with system-level settings...
388
389 // EL3
390 // (no AArch32/64 interprocessing support for now)
391 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
392 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
393 haveSecurity ? 0x1 : 0x0);
394 // EL2

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505 break;
506 case MISCREG_MPIDR_EL1:
507 // @todo in the absence of v8 virtualization support just return MPIDR_EL1
508 return getMPIDR(system, tc) & 0xffffffff;
509 case MISCREG_VMPIDR:
510 // top bit defined as RES1
511 return readMiscRegNoEffect(misc_reg) | 0x80000000;
512 case MISCREG_ID_AFR0: // not implemented, so alias MIDR
494 case MISCREG_ID_DFR0: // not implemented, so alias MIDR
495 case MISCREG_REVIDR: // not implemented, so alias MIDR
496 case MISCREG_MIDR:
497 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
498 scr = readMiscRegNoEffect(MISCREG_SCR);
499 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
500 return readMiscRegNoEffect(misc_reg);
501 } else {
502 return readMiscRegNoEffect(MISCREG_VPIDR);

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544 //b100 - gem5 format is ARMv7
545 ctr.format = 0x4;
546
547 return ctr;
548 }
549 case MISCREG_ACTLR:
550 warn("Not doing anything for miscreg ACTLR\n");
551 break;
513 case MISCREG_REVIDR: // not implemented, so alias MIDR
514 case MISCREG_MIDR:
515 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
516 scr = readMiscRegNoEffect(MISCREG_SCR);
517 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
518 return readMiscRegNoEffect(misc_reg);
519 } else {
520 return readMiscRegNoEffect(MISCREG_VPIDR);

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562 //b100 - gem5 format is ARMv7
563 ctr.format = 0x4;
564
565 return ctr;
566 }
567 case MISCREG_ACTLR:
568 warn("Not doing anything for miscreg ACTLR\n");
569 break;
552 case MISCREG_PMCR:
553 case MISCREG_PMCCNTR:
554 case MISCREG_PMSELR:
555 warn("Not doing anything for read to miscreg %s\n",
556 miscRegName[misc_reg]);
557 break;
570
571 case MISCREG_PMXEVTYPER_PMCCFILTR:
572 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
573 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
574 case MISCREG_PMCR ... MISCREG_PMOVSSET:
575 return pmu->readMiscReg(misc_reg);
576
558 case MISCREG_CPSR_Q:
559 panic("shouldn't be reading this register seperately\n");
560 case MISCREG_FPSCR_QC:
561 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
562 case MISCREG_FPSCR_EXC:
563 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
564 case MISCREG_FPSR:
565 {

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635 // mostly unimplemented, just set NumCPUs field from sim and return
636 L2CTLR l2ctlr = 0;
637 // b00:1CPU to b11:4CPUs
638 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
639 return l2ctlr;
640 }
641 case MISCREG_DBGDIDR:
642 /* For now just implement the version number.
577 case MISCREG_CPSR_Q:
578 panic("shouldn't be reading this register seperately\n");
579 case MISCREG_FPSCR_QC:
580 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
581 case MISCREG_FPSCR_EXC:
582 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
583 case MISCREG_FPSR:
584 {

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654 // mostly unimplemented, just set NumCPUs field from sim and return
655 L2CTLR l2ctlr = 0;
656 // b00:1CPU to b11:4CPUs
657 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
658 return l2ctlr;
659 }
660 case MISCREG_DBGDIDR:
661 /* For now just implement the version number.
643 * Return 0 as we don't support debug architecture yet.
662 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
644 */
663 */
645 return 0;
664 return 0x5 << 16;
646 case MISCREG_DBGDSCRint:
647 return 0;
648 case MISCREG_ISR:
649 return tc->getCpuPtr()->getInterruptController()->getISR(
650 readMiscRegNoEffect(MISCREG_HCR),
651 readMiscRegNoEffect(MISCREG_CPSR),
652 readMiscRegNoEffect(MISCREG_SCR));
653 case MISCREG_ISR_EL1:

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1107 }
1108 }
1109 return;
1110 }
1111
1112 case MISCREG_MIDR:
1113 case MISCREG_ID_PFR0:
1114 case MISCREG_ID_PFR1:
665 case MISCREG_DBGDSCRint:
666 return 0;
667 case MISCREG_ISR:
668 return tc->getCpuPtr()->getInterruptController()->getISR(
669 readMiscRegNoEffect(MISCREG_HCR),
670 readMiscRegNoEffect(MISCREG_CPSR),
671 readMiscRegNoEffect(MISCREG_SCR));
672 case MISCREG_ISR_EL1:

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1126 }
1127 }
1128 return;
1129 }
1130
1131 case MISCREG_MIDR:
1132 case MISCREG_ID_PFR0:
1133 case MISCREG_ID_PFR1:
1134 case MISCREG_ID_DFR0:
1115 case MISCREG_ID_MMFR0:
1116 case MISCREG_ID_MMFR1:
1117 case MISCREG_ID_MMFR2:
1118 case MISCREG_ID_MMFR3:
1119 case MISCREG_ID_ISAR0:
1120 case MISCREG_ID_ISAR1:
1121 case MISCREG_ID_ISAR2:
1122 case MISCREG_ID_ISAR3:

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1438 case MISCREG_TLBI_IPAS2E1_Xt:
1439 assert64(tc);
1440 // @todo: implement these as part of Virtualization
1441 warn("Not doing anything for write of miscreg ITLB_IPAS2\n");
1442 return;
1443 case MISCREG_ACTLR:
1444 warn("Not doing anything for write of miscreg ACTLR\n");
1445 break;
1135 case MISCREG_ID_MMFR0:
1136 case MISCREG_ID_MMFR1:
1137 case MISCREG_ID_MMFR2:
1138 case MISCREG_ID_MMFR3:
1139 case MISCREG_ID_ISAR0:
1140 case MISCREG_ID_ISAR1:
1141 case MISCREG_ID_ISAR2:
1142 case MISCREG_ID_ISAR3:

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1458 case MISCREG_TLBI_IPAS2E1_Xt:
1459 assert64(tc);
1460 // @todo: implement these as part of Virtualization
1461 warn("Not doing anything for write of miscreg ITLB_IPAS2\n");
1462 return;
1463 case MISCREG_ACTLR:
1464 warn("Not doing anything for write of miscreg ACTLR\n");
1465 break;
1446 case MISCREG_PMCR:
1447 {
1448 // Performance counters not implemented. Instead, interpret
1449 // a reset command to this register to reset the simulator
1450 // statistics.
1451 // PMCR_E | PMCR_P | PMCR_C
1452 const int ResetAndEnableCounters = 0x7;
1453 if (newVal == ResetAndEnableCounters) {
1454 inform("Resetting all simobject stats\n");
1455 Stats::schedStatEvent(false, true);
1456 break;
1457 }
1458 }
1459 case MISCREG_PMCCNTR:
1460 case MISCREG_PMSELR:
1461 warn("Not doing anything for write to miscreg %s\n",
1462 miscRegName[misc_reg]);
1466
1467 case MISCREG_PMXEVTYPER_PMCCFILTR:
1468 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
1469 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
1470 case MISCREG_PMCR ... MISCREG_PMOVSSET:
1471 pmu->setMiscReg(misc_reg, newVal);
1463 break;
1472 break;
1473
1474
1464 case MISCREG_HSTR: // TJDBX, now redifined to be RES0
1465 {
1466 HSTR hstrMask = 0;
1467 hstrMask.tjdbx = 1;
1468 newVal &= ~((uint32_t) hstrMask);
1469 break;
1470 }
1471 case MISCREG_HCPTR:

--- 558 unchanged lines hidden --- 		1475 case MISCREG_HSTR: // TJDBX, now redifined to be RES0
1476 {
1477 HSTR hstrMask = 0;
1478 hstrMask.tjdbx = 1;
1479 newVal &= ~((uint32_t) hstrMask);
1480 break;
1481 }
1482 case MISCREG_HCPTR:

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