isa.cc (10204:82d8f37e5b57) isa.cc (10338:8bee5f4edb92)
1/*
1/*
2 * Copyright (c) 2010-2013 ARM Limited
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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594 fpscrMask.fz = ones;
595 fpscrMask.dn = ones;
596 fpscrMask.ahp = ones;
597 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
598 }
599 case MISCREG_NZCV:
600 {
601 CPSR cpsr = 0;
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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594 fpscrMask.fz = ones;
595 fpscrMask.dn = ones;
596 fpscrMask.ahp = ones;
597 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
598 }
599 case MISCREG_NZCV:
600 {
601 CPSR cpsr = 0;
602 cpsr.nz = tc->readIntReg(INTREG_CONDCODES_NZ);
603 cpsr.c = tc->readIntReg(INTREG_CONDCODES_C);
604 cpsr.v = tc->readIntReg(INTREG_CONDCODES_V);
602 cpsr.nz = tc->readCCReg(CCREG_NZ);
603 cpsr.c = tc->readCCReg(CCREG_C);
604 cpsr.v = tc->readCCReg(CCREG_V);
605 return cpsr;
606 }
607 case MISCREG_DAIF:
608 {
609 CPSR cpsr = 0;
610 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif;
611 return cpsr;
612 }

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1683 case MISCREG_TTBR0_EL3:
1684 tc->getITBPtr()->invalidateMiscReg();
1685 tc->getDTBPtr()->invalidateMiscReg();
1686 break;
1687 case MISCREG_NZCV:
1688 {
1689 CPSR cpsr = val;
1690
605 return cpsr;
606 }
607 case MISCREG_DAIF:
608 {
609 CPSR cpsr = 0;
610 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif;
611 return cpsr;
612 }

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1683 case MISCREG_TTBR0_EL3:
1684 tc->getITBPtr()->invalidateMiscReg();
1685 tc->getDTBPtr()->invalidateMiscReg();
1686 break;
1687 case MISCREG_NZCV:
1688 {
1689 CPSR cpsr = val;
1690
1691 tc->setIntReg(INTREG_CONDCODES_NZ, cpsr.nz);
1692 tc->setIntReg(INTREG_CONDCODES_C, cpsr.c);
1693 tc->setIntReg(INTREG_CONDCODES_V, cpsr.v);
1691 tc->setCCReg(CCREG_NZ, cpsr.nz);
1692 tc->setCCReg(CCREG_C, cpsr.c);
1693 tc->setCCReg(CCREG_V, cpsr.v);
1694 }
1695 break;
1696 case MISCREG_DAIF:
1697 {
1698 CPSR cpsr = miscRegs[MISCREG_CPSR];
1699 cpsr.daif = (uint8_t) ((CPSR) newVal).daif;
1700 newVal = cpsr;
1701 misc_reg = MISCREG_CPSR;

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1695 break;
1696 case MISCREG_DAIF:
1697 {
1698 CPSR cpsr = miscRegs[MISCREG_CPSR];
1699 cpsr.daif = (uint8_t) ((CPSR) newVal).daif;
1700 newVal = cpsr;
1701 misc_reg = MISCREG_CPSR;

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