isa.cc (10037:5cac77888310) isa.cc (10188:c09802451018)
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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724 case MISCREG_CNTP_TVAL:
725 case MISCREG_CNTP_TVAL_EL0:
726 return getArchTimer(tc, tc->cpuId())->timerValue();
727 case MISCREG_CNTP_CTL:
728 case MISCREG_CNTP_CTL_EL0:
729 return getArchTimer(tc, tc->cpuId())->control();
730 // PL1 phys. timer, secure
731 // AArch64
1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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724 case MISCREG_CNTP_TVAL:
725 case MISCREG_CNTP_TVAL_EL0:
726 return getArchTimer(tc, tc->cpuId())->timerValue();
727 case MISCREG_CNTP_CTL:
728 case MISCREG_CNTP_CTL_EL0:
729 return getArchTimer(tc, tc->cpuId())->control();
730 // PL1 phys. timer, secure
731 // AArch64
732 case MISCREG_CNTPS_CVAL_EL1:
733 case MISCREG_CNTPS_TVAL_EL1:
734 case MISCREG_CNTPS_CTL_EL1:
732 // case MISCREG_CNTPS_CVAL_EL1:
733 // case MISCREG_CNTPS_TVAL_EL1:
734 // case MISCREG_CNTPS_CTL_EL1:
735 // PL2 phys. timer, non-secure
736 // AArch32
735 // PL2 phys. timer, non-secure
736 // AArch32
737 case MISCREG_CNTHCTL:
738 case MISCREG_CNTHP_CVAL:
739 case MISCREG_CNTHP_TVAL:
740 case MISCREG_CNTHP_CTL:
737 // case MISCREG_CNTHCTL:
738 // case MISCREG_CNTHP_CVAL:
739 // case MISCREG_CNTHP_TVAL:
740 // case MISCREG_CNTHP_CTL:
741 // AArch64
741 // AArch64
742 case MISCREG_CNTHCTL_EL2:
743 case MISCREG_CNTHP_CVAL_EL2:
744 case MISCREG_CNTHP_TVAL_EL2:
745 case MISCREG_CNTHP_CTL_EL2:
742 // case MISCREG_CNTHCTL_EL2:
743 // case MISCREG_CNTHP_CVAL_EL2:
744 // case MISCREG_CNTHP_TVAL_EL2:
745 // case MISCREG_CNTHP_CTL_EL2:
746 // Virtual timer
747 // AArch32
746 // Virtual timer
747 // AArch32
748 case MISCREG_CNTV_CVAL:
749 case MISCREG_CNTV_TVAL:
750 case MISCREG_CNTV_CTL:
748 // case MISCREG_CNTV_CVAL:
749 // case MISCREG_CNTV_TVAL:
750 // case MISCREG_CNTV_CTL:
751 // AArch64
752 // case MISCREG_CNTV_CVAL_EL2:
753 // case MISCREG_CNTV_TVAL_EL2:
754 // case MISCREG_CNTV_CTL_EL2:
751 // AArch64
752 // case MISCREG_CNTV_CVAL_EL2:
753 // case MISCREG_CNTV_TVAL_EL2:
754 // case MISCREG_CNTV_CTL_EL2:
755 panic("Generic Timer register not implemented\n");
755 default:
756 break;
757
758 }
759 return readMiscRegNoEffect(misc_reg);
760}
761
762void
763ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)

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1897 // AArch32
1898 case MISCREG_CNTV_CVAL:
1899 case MISCREG_CNTV_TVAL:
1900 case MISCREG_CNTV_CTL:
1901 // AArch64
1902 // case MISCREG_CNTV_CVAL_EL2:
1903 // case MISCREG_CNTV_TVAL_EL2:
1904 // case MISCREG_CNTV_CTL_EL2:
756 break;
757
758 }
759 return readMiscRegNoEffect(misc_reg);
760}
761
762void
763ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)

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1897 // AArch32
1898 case MISCREG_CNTV_CVAL:
1899 case MISCREG_CNTV_TVAL:
1900 case MISCREG_CNTV_CTL:
1901 // AArch64
1902 // case MISCREG_CNTV_CVAL_EL2:
1903 // case MISCREG_CNTV_TVAL_EL2:
1904 // case MISCREG_CNTV_CTL_EL2:
1905 panic("Generic Timer register not implemented\n");
1906 break;
1907 }
1908 }
1909 setMiscRegNoEffect(misc_reg, newVal);
1910}
1911
1912void
1913ISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint8_t asid, bool secure_lookup,

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1906 }
1907 }
1908 setMiscRegNoEffect(misc_reg, newVal);
1909}
1910
1911void
1912ISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint8_t asid, bool secure_lookup,

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